Datasheet
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011– REVISED JULY 2011
6.3.11 Port PM Status and Control Register (USB 2.0 Ports)
The TUSB73X0 implements a Port PM Status and Control Register for each port that is implemented. The
number of Port PM Status and Control Registers is the same as the value in the MAX_PORTS field in the
Host Controller Structural Parameters 1 Register (see Section 6.2.3).
Operational Base register offset:404h + (10h*(n-1))), where n = Port Number
Register type:Read-Only, Read/Write
Default value: 0000 0000h
Table 6-35. HC Operational Register (Operational Base + 404h + (10h*(n-1))), where n = Port Number
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 6-36. Port PM Status and Control Register (USB 2.0) Description
Bit Field Name Access Description
31:28 PORT_TEST_CTRL rw Port Test Control.
27:16 RSVD r Reserved. Returns zeros when read.
15:8 L1_DEV_SLOT rw L1 Device Slot.
7:4 HIRD rw Host Initiated Resume Duration.
3 RWE rw Remote Wake Enable.
2:0 L1S r L1 Status.
6.3.12 Port Link Info Register
The TUSB73X0 implements a Port Link Info Register for each port USB 3.0 port that is implemented. For
USB 2.0 ports, the Port Link Info Register is reserved and returns zeros when read. The number of Port
Link Info Registers is the same as the value in the MAX_PORTS field in the Host Controller Structural
Parameters 1 Register (see Section 6.2.3).
Operational Base register offset:408h + (10h*(n-1))), where n = Port Number
Register type:Read-Only
Default value: 0000 0000h
Table 6-37. HC Operational Register (Operational Base + 408h + (10h*(n-1))), where n = Port Number
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
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