Datasheet

TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011 www.ti.com
Table 6-10. HC Structural Parameters 3 Description
Bit Field Name Access Description
U2 Device Exit Latency. This field is 07FFh to indicate that the worst
31:16 U2_EXIT_LAT r
case latency for the TUSB73X0 to transition from U2 to U0 is 2047 µs.
15:8 RSVD r Reserved. Returns zeros when read.
U1 Device Exit Latency. This field is 0Ah to indicate that the worst case
7:0 U1_EXIT_LAT r latency for the TUSB73X0 to transition a root hub Port Link State from
U1 to U0 is 10 µs.
6.2.6 Host Controller Capability Parameters
This read only register defines capability parameters supported by the TUSB73X0.
BAR0 register offset: 10h
Register type:Read-Only
Default value: 0270 102Xh
Table 6-11. HC Capability Register 10h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
1 1 1 1 0 0 0 0 0 1 1 0 x 1 0 1
State
Table 6-12. HC Capability Parameters Description
Bit Field Name Access Description
xHCI Extended Capabilities Pointer. This field is 0270h to indicate that
31:16 XECP r the beginning of the first xHCI Extended Capability is at an offset of
09C0h from the address programmed into the Base Address Register 0.
Maximum Primary Stream Array Size. This field is ‘1111’ to indicate that
15:12 MAX_PSA_SIZE r
the TUSB73X0 supports a Primary Stream Array size of 64K.
11:10 RSVD r Reserved. Returns zeros when read.
Secondary Bandwidth Domain Reporting. This bit is ‘0’ to indicate that
9 SBD r the TUSB73X0 does not support Secondary Bandwidth Domain
reporting.
Force Stopped Event. This bit is ‘0’ to indicate that theTUSB73X0 does
8 FSE r
not support Force Stopped Events.
No Secondary SID Support. This bit is ‘0’ to indicate that the TUSB73X0
7 NSS r
supports Secondary Stream ID decoding.
Latency Tolerance Messaging Capability. This bit is ‘1’ to indicate that
6 LTC r
the TUSB73X0 supports Latency Tolerance Messaging.
Light HC Reset Capability. This bit is ‘1’ to indicate that the TUSB73X0
5 LHRC r
supports Light Host Controller Resets.
Port Indicators. This bit is ‘0’ to indicate that the TUSB73X0 does not
4 PIND r
support port indicators.
Port Power Control. This value of this bit is determined by the
3 PPC r
PPC_NOT_PRESENT bit in the USB Control Register.
Context Size. This bit is ‘1’ to indicate that the TUSB73X0 uses 64 byte
2 CSZ r
Context data structures.
Bandwidth Negotiation Capability. This bit is ‘0’ to indicate that the
1 BNC r
TUSB73X0 does not implement Bandwidth Negotiation.
78 xHCI MEMORY MAPPED REGISTER SPACE Copyright © 2011, Texas Instruments Incorporated
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Product Folder Link(s): TUSB7320 TUSB7340