Datasheet
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011– REVISED JULY 2011
5.10 Header Log Register
The Header Log Register stores the TLP header for the packet that lead to the most recently detected
error condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case
of a 4DW TLP header. Each DWORD is stored with the least significant byte representing the earliest
transmitted.
PCI Express Extended Register Offset: 11Ch, 120h, 124h, 128h
Register type:Read-Only
Default value: 0000 0000h
Table 5-16. PCI Express Extended Register 11Ch, 120, 124h, and 128h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
5.11 Device Serial Number Capability ID Register
This read-only register identifies the linked list item as the Device Serial Number Capability. This register
returns 0003h when read.
PCI Express Extended Register Offset: 150h
Register type:Read-Only
Default value: 0003h
Table 5-17. Device Serial Number Capability ID Register
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
State
5.12 Next Capability Offset/Capability Version Register
This read-only register identifies the next location in the PCI Express Extended Capabilities link list. The
upper 12 bits in this register are 000h, indicating that the Device Serial Number Capability is the last
capability in the list. The least significant four bits identify the revision of the current capability block as 1h.
PCI Express Extended Register Offset: 152h
Register type:Read-Only
Default value: 0001h
Table 5-18. Next Capability Offset/Capability Version Register
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
State
Copyright © 2011, Texas Instruments Incorporated PCI EXPRESS EXTENDED CONFIGURATION SPACE 73
Submit Documentation Feedback
Product Folder Link(s): TUSB7320 TUSB7340