Datasheet
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011
www.ti.com
Table 5-5. Custom PHY Transmit/Receive Control Register Description
(1)
(continued)
Flow Control Error. This bit is asserted when a flow control protocol error
13† FC_ERROR † rcu
is detected either during initialization or during normal operation.
12† PSN_TLP † rcu Poisoned TLP. This bit is asserted when a poisoned TLP is received.
11:5 RSVD r Reserved. Returns zeros when read.
Data Link Protocol Error. This bit is asserted if a data link layer protocol
4† DLL_ERROR † rcu
error is detected.
3:0 RSVD r Reserved. Returns zeros when read.
5.5 Uncorrectable Error Mask Register
The Uncorrectable Error Mask Register controls the reporting of individual errors as they occur. When a
bit is set to one, the corresponding error condition will not be logged, and does not update any of the
status bits within the Extended Error Reporting Capability block.
PCI Express Extended Register Offset: 108h
Register type:Read-Only, Read/Write
Default value: 0000 0000h
Table 5-6. PCI Express Extended Register 108h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 5-7. Bit Descriptions – Uncorrectable Error Mask Register
(1)
Bit Field Name Access Description
31:21 RSVD r Reserved. Returns zeros when read.
Unsupported Request Error Mask.
20† UR_ERROR_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
Extended CRC Error Mask.
19† ECRC_ERROR_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
Malformed TLP Mask.
18† MAL_TLP_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
Receiver Overflow Mask.
17† RX_OVERFLOW_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
Unexpected Completion Mask.
16† UNXP_CPL_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
Completer Abort Mask.
15† CPL_ABORT_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
Completion Timeout Mask.
14† CPL_TIMEOUT_MASK † rw 0 – Error Condition is Unmasked
1 – Error Condition is Masked
(1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset
68 PCI EXPRESS EXTENDED CONFIGURATION SPACE Copyright © 2011, Texas Instruments Incorporated
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