Datasheet

TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011 www.ti.com
Table 4-104. Equalizer Control Register Description
(1)
Bit Field Name Access Description
Port 4 Equalizer - Initialization Mode. When the PORT4_EQ_OV bit is
set to ‘1’, these bits are used as the source for the Equalizer init values
31:28† PORT4_EQ_INIT† rw for port 4 of the PHY. For details on the behavior of the equalizer values
refer to Table 8-3. For the TUSB7320 Port 4 is not present and these bits
have no effect.
Port 4 Equalizer- Functional Mode. When the PORT4_EQ_OV bit is set
to ‘1’, these bits are used as the source for the Equalizer func values for
27:24† PORT4_EQ_FUNC† rw port 4 of the PHY. For details on the behavior of the equalizer values
refer to Table 8-3. For the TUSB7320 Port 4 is not present and these bits
have no effect.
Port 3 Equalizer - Initialization Mode. When the PORT3_EQ_OV bit is
set to ‘1’, these bits are used as the source for the Equalizer init values
23:20† PORT3_EQ_INIT† rw for port 3 of the PHY. For details on the behavior of the equalizer values
refer to Table 8-3. For the TUSB7320 Port 3 is not present and these bits
have no effect.
Port 3 Equalizer- Functional Mode. When the PORT3_EQ_OV bit is set
to ‘1’, these bits are used as the source for the Equalizer func values for
19:16† PORT3_EQ_FUNC† rw port 3 of the PHY. For details on the behavior of the equalizer values
refer to Table 8-3. For the TUSB7320 Port 3 is not present and these bits
have no effect.
Port 2 Equalizer - Initialization Mode. When the PORT2_EQ_OV bit is
set to ‘1’, these bits are used as the source for the Equalizer init values
15:12† PORT2_EQ_INIT† rw
for port 3 of the PHY. For details on the behavior of the equalizer values
refer to Table 8-3.
Port 2 Equalizer- Functional Mode. When the PORT2_EQ_OV bit is set
to ‘1’, these bits are used as the source for the Equalizer func values for
11:8† PORT2_EQ_FUNC† rw
port 3 of the PHY. For details on the behavior of the equalizer values
refer to Table 8-3.
Port 1 Equalizer - Initialization Mode. When the PORT1_EQ_OV bit is
set to ‘1’, these bits are used as the source for Equalizer init values for
7:4† PORT1_EQ_INIT† rw
port 1 of the PHY. For details on the behavior of the equalizer values
refer to Error: Reference source not found.
Port 1 Equalizer- Functional Mode. When the PORT1_EQ_OV bit is set
to ‘1’, these bits are used as the source for Equalizer func values for port
3:0† PORT1_EQ_FUNC† rw
1 of the PHY. For details on the behavior of the equalizer values refer to
Table 8-3.
(1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset
4.67 Custom PHY Transmit/Receive Control Register
This register is used to enable the override of the default de-emphasis, transmit swing, and receiver
equalization settings for each of the USB 3.0 ports. This register is reset by a PCI Express reset
(PERST#), a GRST#, or the internally-generated power-on reset.
PCI register offset: ECh
Register type:Read/Write
Default value: 0000 0000h
Table 4-105. PCI Register ECh
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
64 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TUSB7320 TUSB7340