Datasheet
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011– REVISED JULY 2011
4.58 MSI-X Table Offset and BIR Register
This register indicates into which BAR and offset the MSI-X table is mapped.
PCI register offset: C4h
Register type:Read-Only
Default value: 0000 0002h
Table 4-87. PCI Register C4h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
State
Table 4-88. MSI-X Table Offset and BIR Register Description
Bit Field Name Access Description
Table Offset. This field is set to 000h to indicate that the MSI-X
31:3 TABLE_OFFSET r Table is at an offset of 0000h from the beginning of the BAR at offset
18h.
Table BIR. This field is set to 010b to indicate that the MSI-X table is
2:0 TABLE_BIR r
mapped into the BAR at offset 18h.
4.59 MSI-X PBA Offset and BIR Register
This register indicates into which BAR and offset the MSI-X PBA is mapped.
PCI register offset: C8h
Register type:Read-Only
Default value: 0000 1000h
Table 4-89. PCI Register C8h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 4-90. MSI-X PBA Offset and BIR Register Descriptions
Bit Field Name Access Description
PBA Offset. This field is set to 200h to indicate that the MSI-X PBA
31:3 PBA_OFFSET r
is at an offset of 1000h from the beginning of the BAR at offset 18h.
PBA BIR. This field is set to 010b to indicate that the MSI-X PBA is
2:0 PBA_BIR r
mapped into the BAR at offset 18h.
Copyright © 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE 57
Submit Documentation Feedback
Product Folder Link(s): TUSB7320 TUSB7340