Datasheet

TUSB7320, TUSB7340

SLLSE76E–MARCH 2011– REVISED JULY 2011

www.ti.com

4.55 MSI-X Capability ID Register

This read-only register identifies the linked list item as the register for MSI-X Capabilities. The register

returns 11h when read.

PCI register offset: C0h

Default value: 11h

Table 4-83. PCI Register C0h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 0 0 1 0 0 0 1

4.56 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the

TUSB73X0. This register reads 00h indicating that no additional capabilities are supported.

PCI register offset: C1h

Default value: 11h

Table 4-84. PCI Register C1h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 0 0 0 0 0 0 0

4.57 MSI-X Message Control Register

This register is used to control the sending of MSI-X messages.

PCI register offset: C2h

Default value: 0007h

Table 4-85. PCI Register C2h

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

No.

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

State

Table 4-86. MSI-X Message Control Register Description

Bit Field Name Access Description

15 MSIX_EN rw MSI-X Enable.

14 FUNC_MASK rw Function Mask.

13:11 RSVD r Reserved. Returns zero when read.

MSI-X Table Size. This field is set to 07h to indicate a table size of 8

10:0 TABLE_SIZE r

entries.

Submit Documentation Feedback

Product Folder Link(s): TUSB7320 TUSB7340