Datasheet
TUSB7320, TUSB7340
www.ti.com
SLLSE76E–MARCH 2011– REVISED JULY 2011
Table 4-80. GPIO Control Register Description
(1)
Bit Field Name Access Description
15:4 RSVD r Reserved. Returns zero when read.
GPIO 3 Data Direction. This bit selects whether GPIO3 is in input or
output mode.
3† GPIO3_DIR† rw
0 – Input
1 – Output
GPIO 2 Data Direction. This bit selects whether GPIO2 is in input or
output mode.
2† GPIO2_DIR† rw
0 – Input
1 – Output
GPIO 1 Data Direction. This bit selects whether GPIO1 is in input or
output mode.
1† GPIO1_DIR† rw
0 – Input
1 – Output
GPIO 0 Data Direction. This bit selects whether GPIO0 is in input or
output mode.
0† GPIO0_DIR† rw
0 – Input
1 – Output
(1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.
4.54 GPIO Data Register
This register is used to read the state of the GPIO pins and to change the state of GPIO pins that are in
output mode. Writing to a bit that is in input mode will be ignored. The default value at power up depends
on the state of the GPIO terminals as they default to general purpose inputs. This register is reset by a
PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.
PCI register offset: B6h
Register type:Read/Write, Read-Only
Default value: 0000h
Table 4-81. PCI Register B6h
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 x x x x
State
Table 4-82. GPIO Data Register Description
(1)
Bit Field Name Access Description
15:4 RSVD r Reserved. Returns zero when read.
GPIO 3 Data. This bit is used to read the state of GPIO3 or change the
3† GPIO3_DATA† rw
state of GPIO3 in output mode.
GPIO 2 Data. This bit is used to read the state of GPIO2 or change the
2† GPIO2_DATA† rw
state of GPIO2 in output mode.
GPIO 1 Data. This bit is used to read the state of GPIO1 or change the
1† GPIO1_DATA† rw
state of GPIO1 in output mode.
GPIO 0 Data. This bit is used to read the state of GPIO0 or change the
0† GPIO0_DATA† rw
state of GPIO0 in output mode.
(1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.
Copyright © 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE 55
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