Datasheet

TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011 www.ti.com
Table 4-77. PCI Register B3h
Bit No. 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0
Table 4-78. Serial Bus Control and Status Register Description
(1)
Bit Field Name Access Description
Protocol Select. This bit is used to select the serial bus address mode
used.
7† PROT_SEL† rw
0 – Slave Address and Byte Address are sent on the serial bus.
1 – Only the Slave address is sent on the serial bus.
6 RSVD r Reserved. Returns zero when read.
Requested Serial Bus Access Busy. This bit is set when a serial bus
cycle is in progress.
5† REQBUSY† r
0 – No serial bus cycle
1 – Serial bus cycle in progress
Serial EEPROM Access Busy. This bit is set when the serial EEPROM
circuitry in the TUSB73X0 is downloading register defaults from a serial
4† ROMBUSY† r EEPROM.
0 – No EEPROM activity
1 – EEPROM download in progress
Serial EEPROM Detected. This bit is automatically set when a serial
EEPROM is detected by the TUSB73X0. The value of this bit is used to
enable the serial bus interface and to control whether or not the
EEPROM load takes place. Note that a serial EEPROM is only detected
once following a PERST# or a GRST#.
3† SBDETECT† rwu
0 – No EEPROM present, EEPROM load process does not happen
1 – EEPROM present, EEPROM load process takes place
Note that even if a serial EERPOM is not detected following PERST# or
a GRST#, software can still set this bit to enable the serial bus interface.
In this situation, the EEPROM load process will not happen.
Serial Bus Test. This bit is used for internal test purposes. This bit
controls the clock source for the serial interface clock.
2† SBTEST† rw
0 – Serial bus clock at normal operating frequency ~ 100 kHz
1 – Serial bus clock frequency increased for test purposes
Serial Bus Error. This bit is set when an error occurs during a software
initiated serial bus cycle.
1† SB_ERR† rc
0 – No error
1 – Serial bus error
Serial EEPROM Load Error. This bit is set when an error occurs while
downloading registers from a serial EEPROM.
0† ROM_ERR† rc
0 – No Error
1 – EEPROM load error
(1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.
4.53 GPIO Control Register
This register is used to control the direction of the eight GPIO pins. This register is reset by a PCI Express
reset (PERST#), a GRST#, or the internally-generated power-on reset.
PCI register offset: B4h
Register type:Read/Write, Read-Only
Default value: 0000h
Table 4-79. PCI Register B4h
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
54 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011, Texas Instruments Incorporated
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