Datasheet

TUSB7320, TUSB7340

www.ti.com

SLLSE76E–MARCH 2011– REVISED JULY 2011

4.50 Serial Bus Index Register

The value written to the Serial Bus Index register represents the byte address of the byte being read or

written from the serial bus device. The Serial Bus Index register must be written before the before initiating

a serial bus cycle by writing to the Serial Bus Slave Address register. This register is reset by a PCI

Express reset (PERST#), a GRST#, or the internally-generated power-on reset.

PCI register offset: B1h

Default value: 00h

Table 4-74. PCI Register B1h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 0 0 0 0 0 0 0

4.51 Serial Bus Slave Address Regsiter

The Serial Bus Slave Address register is used to indicate the address of the device being targeted by the

serial bus cycle. This register also indicates if the cycle will be a read or a write cycle. Writing to this

a GRST#, or the internally-generated power-on reset.

PCI register offset: B2h

Default value: 00h

Table 4-75. PCI Register B2h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 0 0 0 0 0 0 0

Table 4-76. Serial Bus Slave Address Register Description

(1)

Bit Field Name Access Description

Serial Bus Slave Address. This bit field represents the slave address of a

7:1† SLAVE_ADDR† rw

read or write transaction on the serial interface.

Read/Write Command. This bit is used to determine if the serial bus

cycle will be a read or a write cycle.

0† RW_CMD† rw

0 – A single byte write is requested.

1 – A single byte read is requested.

(1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.

4.52 Serial Bus Control and Status Register

The Serial Bus Control and Status register is used to control the behavior of the Serial bus interface. This

Express reset (PERST#), a GRST#, or the internally-generated power-on reset.

PCI register offset: B3h

Default value: 00h

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