Datasheet

TUSB7320, TUSB7340
www.ti.com SLLSE76E–MARCH 2011– REVISED JULY 2011
Table 4-65. PCI Register 94h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
State
Table 4-66. Device Capabilities 2 Register Description
Bit Field Name Access Description
31:5 RSVD r Reserved. Returns zeros when read.
Completion Timeout Disable Supported. This bit is read only 1b
4 CPLT_TO_DIS_SUP r
indicating that the completion timeout disable mechanism is supported.
Completion Timeout Ranges Supported. This field is read only 0000b
3:0 CPLT_TO_RANGES r
indicating that completion timeout programming is not supported.
4.46 Device Control 2 Register
The Device Control 2 Register controls PCI Express device specific parameters.
PCI register offset: 98h
Register type:Read-only, Read/Write
Default value: 0800h
Table 4-67. PCI Register 98h
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
State
Table 4-68. Device Control 2 Register Description
Bit Field Name Access Description
15:5 RSVD r Reserved. Returns zeros when read.
4 CPTL_TO_DIS rw Completion Timeout Disable.
Completion Timeout Value. This field is read only 0000b indicating that
3:0 CPLT_TO_VALUE r
completion timeout programming is not supported.
4.47 Link Control 2 Register
The Link Control 2 Register indicates is used to control link specific behavior.
PCI register offset: A0h
Register type:Read-only, Read/Write
Default value: 0000h
Table 4-69. PCI Register A0h
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
State
Copyright © 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE 51
Submit Documentation Feedback
Product Folder Link(s): TUSB7320 TUSB7340