Datasheet

TUSB7320, TUSB7340
www.ti.com SLLSE76E–MARCH 2011– REVISED JULY 2011
Table 4-60. Link Capabilities Register Description (continued)
Clock Power Management. This bit is hardwired to 1 to indicate that the
18 CLK_PM r TUSB73X0 supports Clock Power Management through the CLKREQ#
protocol.
L1 Exit Latency. This field indicates the time that it takes to transition
from the L1 state to the L0 state. The value reported by this field is
17:15 L1_LATENCY r
determined by either the L1_EXIT_LAT_ASYNC field or the
L1_EXIT_LAT_COMMON field in the General Control Register 0.
L0s Exit Latency. This field indicates the time that it takes to transition
from the L0s state to the L0 state. The value reported by this field is
14:12 L0S_LATENCY r
determined by either the L0s_EXIT_LAT_ASYNC field or the
L0s_EXIT_LAT_COMMON field in the General Control Register 0.
Active State Link PM Support. This field indicates the level of active state
power management that the TUSB73X0 supports. The value 11b
11:10 ASLPMS r
indicates support for both L0s and L1 through active state power
management.
Maximum Link Width. This field is encoded 000001b to indicate that the
9:4 MLW r
TUSB73X0 only supports a 1x PCI Express link.
Maximum Link Speed. This field is encoded 0010b to indicate that the
3:0 MLS r
TUSB73X0 supports link speeds of 5 Gb/s and 2.5 Gb/s.
4.43 Link Control Register
The Link Control Register indicates is used to control link specific behavior.
PCI register offset: 80h
Register type:Read-only, Read/Write
Default value: 0000h
Table 4-61. PCI Register 80h
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 4-62. Link Control Register Description
Bit Field Name Access Description
15:9 RSVD r Reserved. Returns zeros when read.
8 EN_CPM rw Enable Clock Power Management.
7 ES rw Extended Synch.
Common Clock Configuration. This bit is set when a common clock is
provided to both ends of the PCI Express link. This bit is also used to
select the L0s exit latency and L1 exit latency.
0 – Reference clock is asynchronous (L0s exit latency and L1 exit
6 CCC rw latency based on the L0s_EXIT_LAT_ASYNC and
L1_EXIT_LAT_ASYNC fields in the General Control Register 0)
1 – Reference clock is synchronous (L0s exit latency and L1 exit latency
based on the L0s_EXIT_LAT_COMMON and L1_EXIT_LAT_COMMON
fields in the General Control Register 0)
5 RL r Retrain Link. This bit has no function and is read only zero.
4 LD r Link Disable. This bit has no function and is read only zero.
3 RCB rw Read Completion Boundary.
2 RSVD r Reserved. Returns zero when read.
Copyright © 2011, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE 49
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