Datasheet

TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011 www.ti.com
5.3 Next Capability Offset / Capability Version Register .................................................................. 67
5.4 Uncorrectable Error Status Register .................................................................................... 67
5.5 Uncorrectable Error Mask Register ..................................................................................... 68
5.6 Uncorrectable Error Severity Register .................................................................................. 69
5.7 correctable Error Severity Register ..................................................................................... 70
5.8 correctable Error Mask Register ......................................................................................... 71
5.9 Advanced Error Capabilities and control Register .................................................................... 72
5.10 Header Log Register ...................................................................................................... 73
5.11 Device Serial Number Capability ID Register .......................................................................... 73
5.12 Next Capability Offset/Capability Version Register ................................................................... 73
5.13 Device Serial Number Register .......................................................................................... 74
6 xHCI MEMORY MAPPED REGISTER SPACE ......................................................................... 75
6.1 The xHCI Register Map ................................................................................................... 75
6.2 Host Controller Capability Registers .................................................................................... 75
6.2.1 Capability Registers Length ................................................................................... 75
6.2.2 Host Controller Interface Version Number .................................................................. 76
6.2.3 Host Controller Structural Parameters 1 ..................................................................... 76
6.2.4 Host Controller Structural Parameters 2 ..................................................................... 77
6.2.5 Host Controller Structural Parameters 3 ..................................................................... 77
6.2.6 Host Controller Capability Parameters ....................................................................... 78
6.2.7 Doorbell Offset .................................................................................................. 79
6.2.8 Runtime Register Space Offset ............................................................................... 79
6.3 Host Controller Operational Registers .................................................................................. 80
6.3.1 USB Command Register ...................................................................................... 80
6.3.2 USB Command Register ...................................................................................... 81
6.3.3 USB Status Register ........................................................................................... 81
6.3.4 Page Size Register ............................................................................................. 82
6.3.5 Device Notification Control Register ......................................................................... 83
6.3.6 Command Ring Control Register ............................................................................. 83
6.3.7 Device Context Base Address Array Pointer Register ..................................................... 84
6.3.8 Configure Register .............................................................................................. 85
6.3.9 Port Status and Control Register ............................................................................. 85
6.3.10 Port PM Status and Control Register (USB 3.0 Ports) .................................................... 86
6.3.11 Port PM Status and Control Register (USB 2.0 Ports) .................................................... 87
6.3.12 Port Link Info Register ......................................................................................... 87
6.4 Host Controller Runtime Registers ...................................................................................... 88
6.4.1 Microframe Index Register .................................................................................... 88
6.4.2 Interrupter Management Register ............................................................................ 89
6.4.3 Interrupter Moderation Register .............................................................................. 89
6.4.4 Event Ring Segment Table Size Register ................................................................... 90
6.4.5 Event Ring Segment Table Base Address Register ....................................................... 90
6.4.6 Event Ring Dequeue Pointer Register ....................................................................... 91
6.5 Host Controller Doorbell Registers ...................................................................................... 92
6.6 xHCI Extended Capabilities Registers .................................................................................. 92
6.6.1 USB Legacy Support Capability Register ................................................................... 92
6.6.2 USB Legacy Support Control/Status Register .............................................................. 93
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