Datasheet

TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011 www.ti.com
4.5 Status Register
The status register provides information about the PCI Express interface to the system.
PCI register offset: 06h
Register type:Read-only, Read/Clear
Default value: 0010h
Table 4-6. PCI Register 06h
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
State
Table 4-7. Status Register Description
Bit Field Name Access Description
Detected parity error. This bit is set when the PCI Express interface receives a
poisoned TLP. This bit is set regardless of the state of bit 6 (PERR_ENB) in
15 PAR_ERR rcu the command register (offset 04h, see Section 4.4).
0 = No parity error detected
1 = Parity error detected
Signaled system error. This bit is set when the host controller sends an
ERR_FATAL or ERR_NONFATAL message and bit 8 (SERR_ENB) in the
14 SYS_ERR rcu command register (offset 04h, see Section 4.4) is set.
0 = No error signaled
1 = ERR_FATAL or ERR_NONFATAL signaled
Received master abort. This bit is set when the PCI Express interface of the
host controller receives a completion-with-unsupported-request status.
13 MABORT rcu
0 = Unsupported request not received on the PCI Express interface
1 = Unsupported request received on the PCI Express interface
Received target abort. This bit is set when the PCI Express interface of the
host controller receives a completion-with-completer-abort status.
12 TABORT_REC rcu
0 = Completer abort not received on the PCI Express interface
1 = Completer abort received on the PCI Express interface
Signaled target abort. This bit is set when the PCI Express interface completes
a request with completer abort status.
11 TABORT_SIG rcu
0 = Completer abort not signaled on the PCI Express interface
1 = Completer abort signaled on the PCI Express interface
DEVSEL Timing. These bits are read only zero, because they do not apply to
10:9 DEVSEL_TIMING r
PCI Express.
Master data parity error. This bit is set if bit 6 (PERR_ENB) in the command
register (offset 04h, see Section 4.4) is set and the host controller receives a
completion with data marked as poisoned on the PCI Express interface or
8 DATAPAR rcu
poisons a write request received on the PCI Express interface.
0 = No uncorrectable data error detected on the primary interface
1 = Uncorrectable data error detected on the primary interface.
Fast back-to-back capable. This bit does not have a meaningful context for a
7 FBB_CAP r
PCI Express device and is hardwired to 0b.
6 RSVD r Reserved. Returns zeros when read.
66 MHz capable. This bit does not have a meaningful context for a PCI
5 66MHZ r
Express device and is hardwired to 0b.
Capabilities list. This bit returns 1b when read, indicating that the host
4 CAPLIST r
controller supports additional PCI capabilities.
3 INT_STATUS ru Interrupt Status. This bit reflects the interrupt status of the function.
2:0 RSVD r Reserved. Returns zeros when read.
32 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011, Texas Instruments Incorporated
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