Datasheet

SCL From

Master

1 2 3 7 8 9

SDA Output

By Transmitter

SDA Output

By Receiver

TUSB7320, TUSB7340

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SLLSE76E–MARCH 2011– REVISED JULY 2011

3.2.2 Serial-Bus Interface Protocol

All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a

start condition, which is signaled when the SDA line transitions to the low state while SCL is in the high

state, as illustrated in Figure 3-4. The end of a requested data transfer is indicated by a stop condition,

which is signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3-4.

Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal

during the high state of SCL are interpreted as control signals, that is, a start or stop condition.

Figure 3-4. Serial-Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. During a data transfer operation, the exact number of bytes that

are transmitted is unlimited. However, each byte must be followed by an acknowledge bit to continue the

data transfer operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA

signal low, so that it remains low during the high state of the SCL signal. Figure 3-5 illustrates the

acknowledge protocol.

Figure 3-5. Serial-Bus Protocol Acknowledge

The host controller performs three basic serial-bus operations: single byte reads, single byte writes, and

multibyte reads. The single byte operations occur under software control. The multibyte read operations

are performed by the serial EEPROM initialization circuitry immediately after a PCI Express reset. See

Section 11.6, Serial-Bus EEPROM Application, for details on how the host controller automatically loads

the subsystem identification and other register defaults from the serial-bus EEPROM.

Figure 3-6 illustrates a single byte write. The host controller issues a start condition and sends the 7-bit

slave device address and the R/W command bit is equal to 0b. A 0b in the R/W command bit indicates

that the data transfer is a write. The slave device acknowledges if it recognizes the slave address. If no

acknowledgment is received by the host controller, then bit 1 (SB_ERR) is set in the serial-bus control and

status register (PCI offset BCh, see Section 4.52). Next, the EEPROM word address is sent by the host

controller, and another slave acknowledgment is expected. Then the host controller delivers the data byte

MSB first and expects a final acknowledgment before issuing the stop condition.

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