Datasheet

VDD11

PERST#

VDDA_3P3

and VDD33

PCIE_REFCLK

GRST#

TUSB7320, TUSB7340

SLLSE76E–MARCH 2011– REVISED JULY 2011

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3 FEATURE/PROTOCOL DESCRIPTIONS

3.1 Power-Up/-Down Sequencing

The host controller contains both 1.1-V and 3.3-V power terminals. The following power-up and

power-down sequences describe how power is applied to these terminals.

In addition, the host controller has three resets: PERST#, GRST#, and an internal power- on reset. These

resets are fully described in the next section. The following power-up and power-down sequences

describe how PERST# is applied to the host controller.

The application of the PCI Express reference clock (PCIE_REFCLK) is important to the power-up/-down

sequence and is included in the following power-up and power-down descriptions.

3.1.1 Power-Up Sequence

1. Assert PERST# to the device.

2. Apply 1.1-V and 3.3-V voltages.

3. GRST# must remain asserted until both the 1.1-V and 3.3-V voltages have reached the minimum

recommended operating voltage, see Section 11.2.

4. Apply a stable PCI Express reference clock.

5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two

delay requirements are satisfied:

Wait a minimum of 100 µs after applying a stable PCI Express reference clock. The 100-µs limit satisfies

the requirement for stable device clocks by the de-assertion of PERST.

Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable

power by the de-assertion of PERST.

See the power-up sequencing diagram in Figure 3-1.

Figure 3-1. Power-Up Sequence

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