Datasheet

TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011 www.ti.com
2.7 Terminal Descriptions
The following tables give a description of the terminals. These terminals are grouped in tables by
functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.
TYPE DESCRIPTION
I Input
O Output
I/O Input/Output
PD, PU Internal pull-down/pull-up
S Strapping pin
P Power supply
G Ground
Table 2-2. Clock and Reset Signals
TERMINAL
I/O DESCRIPTION
TUSB7320 TUSB7340
NAME
PIN NO. PIN NO.
Global power reset. This reset brings all of the TUSB73x0 internal registers to their
I
GRST# A15 A15 default states. When GRST# is asserted, the device is completely nonfunctional. GRST#
PU
should be asserted until all power rails are valid at the device.
Crystal input. This terminal is the crystal input for the internal oscillator. The input may
XI A23 A23 I alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ
feedback resistor is required between XI and XO.
Crystal output. This terminal is crystal output for the internal oscillator. If XI is driven by an
XO A22 A22 O external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ
feedback resistor is required between XI and XO.
Frequency select. This terminal indicates the oscillator input frequency and is used to
configure the correct PLL multiplier.
FREQSEL B14 B14 I
If the FREQSEL pin is '0', the frequency used is 48 MHz. If the FREQSEL pin is '1', refer
to Table 4-100: USB Control Register Description.
PCIE_ PCI Express Reference Clock. PCIE_REFCLKP and PCIE_REFCLKN comprise the
REFCLKP A45 A45 differential input pair for the 100-MHz system reference clock.
I
PCIE_ B41 B41
REFCLKN
PCI Express Reset Input. The PERST# signal is used to signal when the system power is
PERST# A40 A40 I
stable. The PERST# signal is also used to generate an internal power on reset
Table 2-3. PCI Express Signals
TERMINAL
I/O DESCRIPTION
TUSB7320 TUSB7340
NAME
PIN NO. PIN NO.
PCIE_TXP B38 B38 O PCI Express transmitter differential pair (positive).
PCIE_TXN A41 A41 O PCI Express transmitter differential pair (negative).
PCIE_RXP B39 B39 I PCI Express receiver differential pair (positive).
PCIE_RXN A42 A42 I PCI Express receiver differential pair (negative).
Wake. Wake is an active low signal that is driven low to reactivate the PCI Express link
hierarchy’s main power rails and reference clocks.
WAKE#
(1)
B35 B35 O
Note: WAKE# is a failsafe I/O and can be connected to a 3.3-V auxiliary supply while
VDD33 is not present.
PCI Express REFCLK Request signal.
CLKREQ#
(1)
B36 B36 O Note: CLKREQ# is a failsafe I/O and can be connected to a 3.3-V auxiliary supply while
VDD33 is not present.
(1) The only failsafe pins in the device are WAKE and CLKREQ#. No other pins are failsafe.
18 OVERVIEW Copyright © 2011, Texas Instruments Incorporated
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Product Folder Link(s): TUSB7320 TUSB7340