Datasheet

TUSB7320, TUSB7340
www.ti.com SLLSE76E–MARCH 2011– REVISED JULY 2011
6.2.4 Host Controller Structural Parameters 2
This read only register defines basic structural parameters supported by the TUSB73X0.
BAR0 register offset: 08h
Register type:Read-Only
Default value: 0C00 00F1h
Table 6-7. HC Capability Register 08h
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1
State
Table 6-8. HC Structural Parameters 2 Description
Bit Field Name Access Description
Max Scratchpad Buffers. This field indicates the number of Scratchpad
31:27 MAX_SCRATCH_BUF r Buffers system software reserves. The TUSB73X0 uses one Scratchpad
Buffer.
Scratchpad Restore. This bit is 1b to indicate that the TUSB73X0
26 SPR r requires the integrity of the Scratchpad Buffer space to be maintained
across power events.
25:13 RSVD r Reserved. Returns zeros when read.
12:8 IOC_INTERVAL r IOC Interval. This field is 0b.
Event Ring Segment Table Max. This field is 1111b to indicate that the
7:4 ERST_MAX r
TUSB73X0 supports up to 32K Event Ring Segment Table entries.
Isochronous Scheduling Threshold. This field is 0001b to indicate that
3:0 IST r software can add a TRB no later than 1 Microframes before that TRB is
scheduled to be executed.
6.2.5 Host Controller Structural Parameters 3
This read only register defines basic structural parameters supported by the TUSB73X0.
BAR0 register offset: 0Ch
Register type:Read-Only
Default value: 07FF 00A0h
Table 6-9. HC Capability Register 0Ch
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
No.
Reset
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
State
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
No.
Reset
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
State
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Product Folder Link(s): TUSB7320 TUSB7340