Datasheet

TUSB7320, TUSB7340

SLLSE76E–MARCH 2011– REVISED JULY 2011

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4.34 Serial Bus Release Number Register (SBRN)

This read only register is set to 30h to indicate that the TUSB73X0 is compliant to release 3.0 of the

Universal Serial Bus Specification.

PCI register offset: 60h

Default value: 00h

Table 4-46. PCI Register 60h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 0 1 1 0 0 0 0

4.35 Frame Length Adjustment Register (FLADJ)

This register is used to adjust any offset from the clock source that generates the clock that drives the

SOF counter. When a new value is written to this register, the length of the frame is adjusted for all USB

buses implemented by the TUSB73X0. This register is only reset by a Global Reset.

PCI register offset: 61h

Default value: 20h

Table 4-47. PCI Register 61h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 0 1 0 0 0 0 0

Table 4-48. Frame Length Adjustment Register Description

Bit Field Name Access Description

7:6 RSVD r Reserved. Return zeros when read.

Frame Length Timing Value. Each decimal value change to this register

corresponds to 16 high-speed bit times. The SOF cycle time is equal to

5:0 FRAME_LENGTH * rw

59488 plus the value in this field. The default value is decimal 32 (20h),

which gives a SOF cycle time of 60000.

4.36 PCI Express Capability ID Register

This read-only register identifies the linked list item as the register for PCI Express Capabilities. The

PCI register offset: 70h

Default value: 10h

Table 4-49. PCI Register 70h

Bit No. 7 6 5 4 3 2 1 0

Reset State 0 0 0 1 0 0 0 0

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Product Folder Link(s): TUSB7320 TUSB7340