Datasheet
TUSB7320, TUSB7340
SLLSE76E–MARCH 2011– REVISED JULY 2011
www.ti.com
Table 2-4. USB Downstream Signals (continued)
TERMINAL
I/O DESCRIPTION
TUSB7320 TUSB7340
NAME
PIN NO. PIN NO.
USB DS Port 3 Power On Control for Downstream Power. The terminal is used for
O control of the downstream power switch. If the PWRON_POLARITY bit is set to ‘1’, this
PWRON3# N/A A46
PD pin is active high and the internal pull-down is disabled. This pin may be at low
impedance when power rails are removed.
USB DS Port 3 Over-Current Detection.
I
OVERCUR3# N/A B43 0: over-current detected;
PU
1: over-current not detected
USB SuperSpeed transmitter differential pair (positive).
USB_SSTXP_
N/A B7 O Note: When routing, it is permissible to swap the positive and negative signals in Port 4
DN4
SSTX differential pair.
USB SuperSpeed transmitter differential pair (negative).
USB_SSTXN_
N/A A8 O Note: When routing, it is permissible to swap the positive and negative signals in Port 4
DN4
SSTX differential pair.
USB SuperSpeed receiver differential pair (positive).
USB_SSRXP_
N/A B6 I Note: When routing, it is permissible to swap the positive and negative signals in Port 4
DN4
SSRX differential pair.
USB SuperSpeed receiver differential pair (negative).
USB_SSRXN_
N/A A7 I Note: When routing, it is permissible to swap the positive and negative signals in Port 4
DN4
SSRX differential pair.
USB_DP_DN4 N/A B5 I/O USB High-speed differential transceiver (positive).
USB_DM_DN4 N/A A5 I/O USB High-speed differential transceiver (negative).
USB DS Port 4 Power On Control for Downstream Power. The terminal is used for
O control of the downstream power switch. If the PWRON_POLARITY bit is set to ‘1’, this
PWRON4# N/A A48
PD pin is active high and the internal pull-down is disabled. This pin may be at low
impedance when power rails are removed.
USB DS Port 4 Over-Current Detection.
I
OVERCUR4# N/A B45 0: over-current detected;
PU
1: over-current not detected
Table 2-5. I
2
C Signals
TERMINAL
I/O DESCRIPTION
TUSB7320 TUSB7340
NAME
PIN NO. PIN NO.
SCL B2 B2 I/O I
2
C Clock - If no I
2
C device is present, pull this line down to disable.
SDA A2 A2 I/O I
2
C Data - If no I
2
C device is present, pull this line down to disable.
Table 2-6. Test and Miscellaneous Signals
TERMINAL
I/O DESCRIPTION
TUSB7320 TUSB7340
NAME
PIN NO. PIN NO.
I
JTAG_TCK A32 A32 JTAG test clock
PD
I
JTAG_TDI A35 A35 JTAG test data in
PU
O
JTAG_TDO B31 B31 JTAG test data out
PD
I
JTAG_TMS B30 B30 JTAG test mode select
PU
I
JTAG_RST# B32 B32 JTAG reset. Should be pulled low for normal operation.
PD
20 OVERVIEW Copyright © 2011, Texas Instruments Incorporated
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