Datasheet
ATA/ATAPI Interface Port
11−18
SLLS535E − March 2008TUSB6250
Table 11−5. Multiword DMA Mode and Timing Correlation Chart
CYCLE TIME (t
0
) ASSERTION TIME (t
D
) RECOVERY TIME (t
K
)
MWDMA
TRANSFER
MODE
TIME
(ns)
TIME
(ns)
# OF CLKS (SEE
NOTE 1)
TIME
(ns)
# OF CLKS (SEE
NOTE 1)
TRANSFER
MODE
SPEC
(MIN)
ACTUAL
SPEC
(MIN)
ACTUAL
REGISTER
SETTING
ACTUAL
SPEC
(MIN)
ACTUAL
REGISTER
SETTING
ACTUAL
0 480 483.43 215 216.71 12 13 250 266.72 14 16
1 150 150.03 80 83.35 4 5 50 66.68 2 4
2 120 133.36 70 83.35 4 5 25 50.01 1 3
Other N/A 483.43 N/A 216.71 12 13 N/A 266.72 14 16
NOTES: 1. All the actual timing listed is based on the 60-MHz clock cycle (16.67 ns) used in the TUSB6050.
• The spec value listed is based on the ATA/ATAPI-5 specification.
• The actual recovery time is obtained with the consideration to meet both the cycle time and recovery time value specified in the
ATA/ATAPI-5 specification, after meeting the assertion time.
• Because the TUSB6250 hardware always adds one extra clock cycle to the assertion time value and two extra clock cycles to the
recovery time value, the TUSB6250 firmware must use one less than the desired number of clock cycles for any assertion time and
two less for any recovery time programming value. For example, to achieve 216.71-ns assertion and a 266.72-ns recovery time for
MWDMA mode 0, instead of using 13 clock cycles as the assertion and 16 clock cylces as the recovery time value, the firmware
must use only 12 clock cycles as assertion time and 14 clock cycles as the recovery time programming value.
• According to the ATA/ATAPI-5 specification, the TUSB6250 firmware can issue an IDENTIFY DEVICE command to determine the
supported modes of the mass storage device and then use the corresponding timing in this table during the data transfer.
Table 11−6. Ultra DMA Mode and Timing Correlation Chart (Applies to UDMA Write Only)
CYCLE TIME ASSERTION TIME (t
CYC
) RECOVERY TIME (t
RP
)
UDMA
TRANSFER
TIME
(ns)
TIME
(ns)
# OF CLKS (SEE
NOTE 1)
TIME
(ns)
# OF CLKS (SEE
NOTE 1)
TRANSFER
MODE
SPEC
(MIN)
ACTUAL
SPEC
(MIN)
ACTUAL
REGISTER
SETTING
ACTUAL
SPEC
(MIN)
ACTUAL
REGISTER
SETTING
ACTUAL
(SEE
NOTE 4)
0 224 233.38 112 116.69 5 7 160 166.7 9 10
1 146 166.7 73 83.35 3 5 125 133.36 7 8
2 108 133.36 54 66.68 2 4 100 100.02 5 6
3 78 100.02 39 50.01 1 3 100 100.02 5 6
4 50 66.68 25 33.34 0 2 100 100.02 5 6
Other N/A 233.38 N/A 116.69 5 7 N/A 166.7 9 10
NOTES: 1. All the actual timing listed is based on the 60-MHz clock cycle (16.67 ns) used in the TUSB6050.
• The spec value listed is based on the ATA/ATAPI-5 specification.
• ATA/ATAPI-5 specification does not define cycle time for UDMA data transfer. The cycle time is used here for easy comparison with
PIO and MWDMA mode, which equals twice the assertion time.
• The actual recovery time t
RP
has an actual overhead of one to three clock cycles. What is listed in this table is the minimum value.
It should be noted that the recovery time has no contribution to the cycle time in the UDMA data transfer, because it only affects the
timing when pausing a UDMA data transfer.
• The firmware must use two less clock cycles than the desired number of clock cycles for the assertion time and one less clock cycles
for the recovery time programming value.