Datasheet

ATA/ATAPI Interface Port
11−16
SLLS535E − March 2008TUSB6250
11.5.13 PIOSPRC: PIO Transfer Speed (Recovery Time) Register (XDATA at F0DD)
The PIOSPRC register contains PIO transfer speed (recovery time) along with write data hold time
information. The PIOSPRC register is cleared by a power-up or a WDT reset. A USB reset cannot reset the
PIOSPRC register.
The unit of recovery time is defined as a single cycle of a 60-MHz clock (16.67 ns), which reflects the t
2i
parameter value in an actual ATA/ATAPI drive (see the ATA/ATAPI-5 specification, page 293). The TUSB6250
state machine automatically adds two extra clock cycles to the setup value. Therefore, a 0−31 value in the
PIOSPRC register is corresponding to 2−33 actual clock cycles of PIO transfer recovery time.
The TUSB6250 has a fixed two-clock-cycle (33.334 ns) write data hold time in PIO mode, mentioned
previously.
76543210
RSV RSV RSV PRCVT
4
PRCVT
3
PRCVT
2
PRCVT
1
PRCVT
0
R/O R/O R/O R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
4−0 PRCV[4:0] 00000 PIO transfer speed (recovery time) in the unit of a 60-MHz clock cycle.
7−5 RSV 000 Reserved
11.5.14 DMASPAS: DMA Transfer Speed (Assertion Time) Register (XDATA at F0DE)
The DMASPAS register contains the DMA (including multiword DMA and ultra DMA) transfer speed (assertion
time) information. The DMASPAS register can be cleared by a power-up or a WDT reset. A USB reset cannot
reset the DMASPAS register.
The assertion time is defined in the unit of a 60-MHz clock cycle (16.67 ns), which shall reflect the t
d
parameter
(for multiword DMA) or t
CYC
parameter (for ultra DMA) value in an actual ATA/ATAPI drive (see the
ATA/ATAPI-5 specification, page 294 and 300).
The TUSB6250 state machine automatically adds extra clock cycle(s) to the assertion time setup value based
on the DMA mode used:
• Multiword DMA: one extra clock cycle
• Ultra DMA: two extra clock cycles
Therefore, a 0−31 value in the DMASPAS register is corresponding to 1−32 clock cycles of multiword DMA
transfer assertion time or 2−33 clock cycles of ultra DMA transfer assertion time.
The TUSB6250 has a fixed one 60-MHz clock-cycle (16.67 ns) write data hold time for the ultra DMA write
data transfer, which is part of the additional two extra clock cycle assertion time mentioned previously.
76543210
DIRSNDEN RSV RSV DAST4 DAST3 DAST2 DAST1 DAST0
R/W R/O R/O R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
4−0 DAST[4:0] 00000 DMA transfer speed (assertion time) in the unit of 60-MHz clock cycle.
6−5 RSV 00 Reserved
7 DIRSNDEN 0 Enables sending the DMA transfer direction bit to the ATAPI device.
This bit, when set, allows the TUSB6250 ATA/ATAPI state machine to automatically send the
DMA data transfer direction information to the ATAPI device during the DMA auto data transfer.
This bit is only useful in the ATAPI (not ATA) DMA auto data transfer. This feature is disabled as
a power-up default.
11.5.15 DMASPRC: DMA Transfer Speed (Recovery Time) Register (XDATA at F0DF)
The DMASPRC register contains the DMA (including multiword DMA and ultra DMA) transfer speed (recovery
time) and write data hold time information. The DMASPRC register is cleared by a power up or a WDT reset.
A USB reset cannot reset the DMASPRC register.