Datasheet

ATA/ATAPI Interface Port
11−15
SLLS535E − March 2008 TUSB6250
11.5.11 CMNDLNGTH: Command Length Register (XDATA at F0DA)
76 543210
RSV ATP_TRANS_DONE ATP_DIS CMD_LENG4 CMD_LENG3 CMD_LENG2 CMD_LENG1 CMD_LENG0
R/O R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
4−0 CMD_LENG[4:0] 00h Command length[4:0]. These bits are only used by the ATAPI device during the fully
automatic mode, when the AUTO_CMD bit is set in the ATPIFCNFG1 register.
CMD_LENG[4:0] tells the internal state machines how many bytes from Task_File0 to
Task_File15 must be transferred to the ATAPI data register as the command packet.
In the ATA fully automatic mode, the TUSB6250 ATA/ATAPI controller state machine
always fetches the ATA command block register value from the Task_File1 to
Task_File7 registers and ignores the setting of the CMD_LENG bits.
5 ATP_DIS 1 ATA/ATAPI bus disable.
When this bit is set (ATP_DIS = 1), all output terminals of the TUSB6250 ATA/ATAPI bus
are put in the high-impedance state, which is also the power-up default. The MCU must
clear this bit at the appropriate time after the power-up reset of the TUSB6250 to enable
the ATA/ATAPI bus outputs.
 This bit has no control of the TUSB6250 ATA/ATAPI state machine. It only puts the
ATA/ATAPI bus in the high--state.
 This bit can only put the RST_ATA
pin in 3-state when the HARD_RST bit (in
ATPIFCNFG1 register) is not true. When the HARD_RST bit is true, the RST_ATA
pin is driven low.
6 ATP_TRANS_DONE 0 ATA/ATAPI transfer done. This bit is only used in semi-auto mode and fully-auto mode
data transfer. It is used by the firmware to notify the transaction state machine that the
MCU isi attempting to terminate the data transfer, so that the state machine hanging can
be avoided in case any transfer byte-count mismatch occurs.
The MCU can set this bit (ATP_TRANS_DONE = 1) to force the transaction state
machine back to the idle state. When using this bit, the MCU shall make sure the
transaction state machine goes back to the idle state (TRANS_STATE[4:0]=0x00 in the
ATA transaction state register) before clearing ATP_TRANS_DONE to 0 to terminate
the data transfer.
7 RSV 0 This bit must be set to 0 during normal operation.
11.5.12 PIOSPAS: PIO Transfer Speed (Assertion Time) Register (XDATA at F0DC)
The PIOSPAS register contains the PIO transfer speed (assertion time) information. The PIOSPAS register
can be cleared by a power up or a WDT reset. A USB reset cannot reset the PIOSPAS register.
The assertion time is defined in the unit of a 60-MHz clock cycle (16.67 ns), which reflects the t
2
parameter
value in an actual ATA/ATAPI drive (see the ATA/ATAPI-5 specification, page 293). The TUSB6250 state
machine automatically adds one extra clock cycle to the setup value. Therefore, a 0−31 value in the register
is corresponding to 1−32 clock cycles of PIO transfer assertion time.
7 6543210
USB_STATE_RST RSV RSV PAST4 PST3 PAST2 PAST1 PAST0
W/O R/O R/O R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
4−0 PAST[4:0] 00000 PIO transfer speed (assertion time) in the unit of a 60-MHz clock cycle.
6−5 RSV 00 Reserved
7 USB_STATE_RST 0 USB state machine reset.
This bit is used by the MCU to notify the USB state machine that the MCU is attempting
to terminate the data transfer, so that state machine hanging can be avoided in case any
transfer byte-count mismatch occurs.
The MCU can set this bit (USB_STATE_RST= 1) to force the USB state machine back to
the idle state. This bit is write-only and always read back as 0.