Datasheet

ATA/ATAPI Interface Port
11−13
SLLS535E − March 2008 TUSB6250
Table 11−3 shows the register address map for the command and control block registers used in the ATA and
ATAPI devices.
Table 11−3. ATA and ATAPI Command and Control Block Registers
ATP_ADR
ATP_ADR
ATA PROTOCOL ATAPI PROTOCOL
ATP_ADR
[3]
ATP_ADR
[2:0]
READ WRITE READ WRITE
CONTROL BLOCK REGISTER
0
(CS1
pin asserted)
110 Alternate status Device control Alternate status Device control
COMMAND BLOCK REGISTER
000 Data register Data register
001 Error register Feature register Error register Feature register
010 Sector count Interrupt reason
1
011 Sector number
1
(CS0 pin asserted)
100 Cylinder low Byte count low
(CS0 pin asserted)
101 Cylinder high Byte count high
110 Device/head Device select
111 Status Command Status Command
NOTE: The other addressable spaces not listed in the table are either reserved, not used, or obsolete addresses according to the ATA/ATAPI-5
specification. It is the application firmware’s responsibility to ensure not to access those spaces. However, if developers must implement
some vendor-specific function in those spaces, the TUSB6250 hardware does not restrict such access and still allows the transfer to go
through.
11.5.6 ATPACSREG3: ATA/ATAPI Access Register 3 (XDATA at F0D5)
76543210
SECT_CNT7 SECT_CNT6 SECT_CNT5 SECT_CNT4 SECT_CNT3 SECT_CNT2 SECT_CNT1 SECT_CNT0
R/O R/O R/O R/O R/O R/O R/O R/O
BIT
NAME RESET FUNCTION
0 SECT_CNT[7:0] 00h Sector count[7:0] is the lower 8 bits of SEC_CNT[8:0], which contains the read-only sector
count value used by the ATA PIO data transfer only.
The SEC_CNT[8:0] initial value:
 Comes from TRNS_BCN[17:9] when the MCU first loads the initial transfer byte-count
value.
 Should be consistent with the meaning of the ATA sector count register in the ATA PIO
mode.
After transferring each sector data (512 bytes), SEC_CNT[8:0] is decremented by 1. If the
command execution is terminated normally, the final value of sector count[8:0] should
become 0.
11.5.7 TRANSBCNT0: USB or ATA/ATAPI Transfer Byte-Count Register 0 (XDATA at
F0D6)
There are two physical sets of transfer byte-count registers in the TUSB6250, which share the same address
range from 0xF0D6 to 0xF0D9.
• The USB transfer byte-count register 0−3, which is used to count the data transferred across the USB
interface.
• The ATA/ATAPI transfer byte-count register 0−3, which is used to count the data transferred across the
ATA/ATAPI interface.
When the MCU performs write access to these registers (0xF0D6–0xF0D9), both the USB transfer byte-count
register 0−3 and the ATA/ATAPI transfer byte-count register 0−3 are loaded with the same initial value. For
read access to either set of these registers, the MCU must set the UABYCNAB bit in the ATPIFCNFG0 register
to select read access to a particular register set.