Datasheet

ATA/ATAPI Interface Port
11−12
SLLS535E − March 2008TUSB6250
11.5.3 ATPACSREG0: ATA/ATAPI Access Register 0 (XDATA at F0D2)
ATPACSREG1 and ATPACSREG0 are the ATA/ATAPI register access holding registers. For register write
transfer, this register set contains the data to be written to a register.
For register read transfer, after the ATA/ATAPI register read transfer is done, ATP_DATA[15:0] contains the
read value.
• If the read transfer does not access the data register, only ATP_DATA[7:0] contains valid data.
• If the read transfer accesses the data register, ATP_DATA[15:0] contains valid data.
76543210
ATP_DATA7 ATP_DATA6 ATP_DATA5 ATP_DATA4 ATP_DATA3 ATP_DATA2 ATP_DATA1 ATP_DATA0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 ATP_DATA[7:0] 00h ATA/ATAPI register access holding register low-byte value.
11.5.4 ATPACSREG1: ATA/ATAPI Access Register 1 (XDATA at F0D3)
76543210
ATP_DATA15 ATP_DATA14 ATP_DATA13 ATP_DATA12 ATP_DATA11 ATP_DATA10 ATP_DATA9 ATP_DATA8
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 ATP_DATA[15:8] 00h ATA/ATAPI register access holding register high-byte value.
11.5.5 ATPACSREG2: ATA/ATAPI Access Register 2 (XDATA at F0D4)
765432 1 0
ATP_ADR3 ATP_ADR2 ATP_ADR1 ATP_ADR0 ATP_WR ATP_RD CLR_SECFIFO SECT_CNT8
R/W R/W R/W R/W W/C W/C W/C R/O
BIT
NAME RESET FUNCTION
0 SECT_CNT8 0 Sector count[8] is the most significant bit of SEC_CNT[8:0], which contains the read-only
sector count value used by the ATA PIO data transfer only. See ATA/ATAPI access register
3 for detailed information.
1 CLR_SECFIFO 0 Clear sector FIFO. Set by the MCU. Self-cleared one clock cycle later.
When this bit is set (CLR_SECFIFO = 1), the internal logic clears all sector FIFO pointers back
to 0 to make the sector FIFO completely empty and clears all the internal data buffers.
If data transfer through sector FIFO is not terminated normally, the MCU must set this bit to
1. Otherwise, the next ATA/ATAPI command execution may carry residue data from the
current command.
2 ATP_RD 0 ATA/ATAPI bus read. Set by the MCU. Self-cleared when the register read transfer is finished.
When this bit is set (ATP_RD = 1), the ATA/ATAPI register read transfer starts.
 After the register read transfer is done, both ATP_RD and ATP_WR are cleared to 0
automatically and the register read data is stored in ATP_DATA[15:0].
 If both ATP_RD and ATP_WR are set to 1 by the MCU, only the register read transfer is
carried out. The register write transfer is ignored.
3 ATP_WR 0 ATA/ATAPI bus write. Set by the MCU. Self-cleared when register write transfer is finished.
When this bit is set (ATP_WR = 1), the ATA/ATAPI register write transfer starts with the write
data stored in ATP_DATA[15:0].
After the register read transfer is done, both ATP_RD and ATP_WR are cleared to 0
automatically.
7−4 ATP_ADR[3:0] 0h ATA/ATAPI address[3:0] is used as the address to access the ATA/ATAPI command block
registers and the ATA/ATAPI control block registers during register read or write access.
 If ATP_ADR[3] = 0, the access is for ATA/ATAPI command block registers. ATP_ADR[2:0]
is used to select one particular register among the ATA/ATAPI command block registers.
 If ATP_ADR[3] = 1, the access is for ATA/ATAPI control block registers. ATP_ADR[2:0] is
used to select one particular register among the ATA/ATAPI control block registers.
Only the data register is 16-bit access. All other registers are 8-bit access.
The internal state machine doesn’t constrain the access to a reserved register.