Datasheet

ATA/ATAPI Interface Port
11−11
SLLS535E − March 2008 TUSB6250
11.5.2 ATPIFCNFG1: ATA/ATAPI Interface Configuration Register 1 (XDATA at F0D1)
76543 2 1 0
ATP_MOD SOFT_RST HARD_RST XFER_DIR AUTO_CMD START_ATAPI NON_DA_CMD DEV_SEL
R/W W/C R/W R/W R/W W/C R/W R/W
BIT
NAME RESET FUNCTION
0 DEV_SEL 0 ATAPI device select.
When ATP_MOD = 1 and AUTO_CMD =1 and START_ATAPI =1 and:
DEV_SEL = 0 The internal state machine sets the DEV bit of the device/head register to 0 when
it sends the packet command.
DEV_SEL = 1 The internal state machine sets the DEV bit of the device/head register to 1 when
it sends the packet command.
1 NON_DA_CMD 0 Non-data command.
When START_ATAPI = 1 and:
NON_DA_CMD = 0 The internal state machine expects to transfer data between the TUSB6250
and the storage device.
NON_DA_CMD = 1 The internal state machine does not transfer data.
2 START_ATAPI 0 Start ATA/ATAPI transfer. Set by the MCU/self-cleared.
When this bit is set (START_ATAPI = 1), the internal state machine starts:
 Sending a command if AUTO_CMD = 1
 Transferring data if AUTO_CMD = 0
START_ATAPI remains active for one clock cycle. It is cleared thereafter automatically.
The data transfer size is determined by the transfer byte count TRNS_BCN[31:0].
3 AUTO_CMD 0 Auto command.
When this bit is set (AUTO_CMD = 1), the internal state machine automatically fetches the CBW
command and command parameters from Task_File0 to Task_File15, which is loaded to the
storage device to start the command execution once the MCU sets START_ATAPI to 1.
4 XFER_DIR 0 ATA/ATAPI data transfer direction.
XFER_DIR = 0 Data transfer is from the host (TUSB6250) to the storage device.
XFER_DIR = 1 Data transfer is from the storage device to the host (TUSB6250).
5 HARD_RST 0 ATA/ATAPI hardware reset. Set and cleared by the MCU.
When this bit is set (HARD_RST = 1), the TUSB6250 drives the RST_ATA
pin low, which creates
a hard reset to the storage device. To dismiss a hard reset to the storage device, the MCU must
write a 0 to the HARD_RST bit.
6 SOFT_RST 0 ATA/ATAPI state machine soft reset. Set by the MCU/self cleared.
When this bit is set (SOFT_RST = 1), the internal logic generates a soft reset to:
 Reset the internal state machines,
 Reset sector FIFO pointers (to 0),
 Clear the internal data buffer.
The internal soft reset signal lasts one clock cycle. The SOFT_RST bit is automatically cleared
to 0 thereafter. The SOFT_RST bit has nothing to do with any reset function to the ATA/ATAPI
device.
7 ATP_MOD 0 ATAPI mode.
ATP_MOD = 0 The storage device uses ATA transfer protocol.
ATP_MOD = 1 The storage device uses ATAPI transfer protocol.