Datasheet

ATA/ATAPI Interface Port
11−10
SLLS535E − March 2008TUSB6250
7 654 3 2 1 0
UABYCNAB RSV RSV RSV USBWPNABRTEN DMADIRCKEN TRANS_MOD1 TRANS_MOD0
R/W R/O R/O R/O R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
1−0 TRANS_MOD[1:0] 00 ATA/ATAPI transfer mode.
TRANS_MOD = 00 PIO mode
TRANS_MOD = 01 Multiword DMA mode
TRANS_MOD = 10 Reserved
TRANS_MOD = 11 Ultra DMA mode
2 DMADIRCKEN 0 DMA direction check enable.
This bit, when set, enables the TUSB6250 state machine to check the DMA transfer
direction matching between the TUSB6250 and the ATAPI device automatically before
performing the ATAPI DMA data transfer. If there is a mismatch in DMA data transfer
direction, the data transfer is aborted and the ATP_DSEQ_ER in the ATPINTRPT1 register
is set to indicate the error. This bit is not used in ATA data transfer.
3 USBWPNABRTEN 0 USB write pending abort enable.
During a write data transfer to an ATA/ATAPI device, if any byte-count mismatch occurs at
the USB interface side of the TUSB6250 the process of moving the last received data packet
from the sector FIFO to an ATA/ATAPI device is paused to wait for the MCU decision.
This bit, when set, allows the MCU to abort and flush the last received packet into the sector
FIFO.
This bit, when cleared, allows the MCU to move all the data stored in sector FIFO to an
ATA/ATAPI device up to the dCBWDataTransferLength.
The MCU must ensure it sets this bit properly before clearing the USB_XFR_PND interrupt.
6−4 RSV 000 These three bits must be set to 000 during normal operation.
7 UABYCNAB 0 USB or ATA/ATAPI byte-count register access control bit.
UABYCNAB = 0 Enables read access to the USB byte-count register (0xF0D6–0xF0D9).
UABYCNAB = 1 Enables read access to the ATAPI byte-count register (0xF0D6–0xF0D9).