Datasheet

ATA/ATAPI Interface Port
11−9
SLLS535E − March 2008 TUSB6250
• If the AUTO_CMD bit is not set (implies the fully-auto mode is not used):
The Task_File0 to Task_File15 registers are not used by the transaction state machine of the ATA/ATAPI
controller. The MCU is responsible to write command block registers manually to set up the command,
read the status register to check if the device is busy or any error condition has occurred, and transfer
command packets if the device is an ATAPI device.
After the MCU finishes the command setup, setting START_ATAPI to 1 in the semiautomatic mode (the
AUTO_CMD bit is not set, but the MAP_SECF bit is set) causes the transaction state machine to start data
transfer if the command is not a nondata command and there is no error.
11.5 ATA/ATAPI Group 1 Registers
Table 11−2. Group 1 Registers
MMR
ADDRESS
Offset Address
(Base Address = F0C0)
REGISTER DESCRIPTION
F0D0 10h ATA/ATAPI interface configuration register 0
F0D1 11h ATA/ATAPI interface configuration register 1
F0D2 12h ATA/ATAPI access register 0
F0D3 13h ATA/ATAPI access register 1
F0D4 14h ATA/ATAPI access register 2
F0D5 15h ATA/ATAPI access register 3
F0D6 16h Transfer byte-count register 0 (7:0)
F0D7 17h Transfer byte-count register 1 (15:8)
F0D8 18h Transfer byte-count register 2 (23:16)
F0D9 19h Transfer byte-count register 3 (31:24)
F0DA 1Ah Command length register
F0DB 1Bh Block sector count register
F0DC 1Ch PIO transfer speed (assertion time) register
F0DD 1Dh PIO transfer speed (recovery time) register
F0DE 1Eh DMA transfer speed (assertion time) register
F0DF 1Fh DMA transfer speed (recovery time) register
11.5.1 ATPIFCNFG0: ATA/ATAPI Interface Configuration Register 0 (XDATA at F0D0)
The ATPIFCNFG0 register contains ATA/ATAPI interface configuration information and is cleared by a power
up or a WDT reset. A USB reset cannot reset the ATPIFCNFG0 register.
The UABYCNAB bit is used to enable read access to the USB or ATA/ATAPI transfer byte-count registers (set),
which share the same addresses at 0xF0D6–0xF0D9. Before accessing a particular register set between the
two, the firmware must set this bit to a certain value. To avoid overwriting the value of other bits, the firmware
must read the contents of the ATPIFCNFG0 register, change the UABYCNAB bit to write the bit[6:0] value of
the read content, and then write the result back to the ATPIFCNFG0 register.