Datasheet

ATA/ATAPI Interface Port
11−7
SLLS535E − March 2008 TUSB6250
• Semiautomatic mode—In this mode, similar to the fully manual mode, the MCU is also responsible for
handling all data movement between the 4K-byte EDB and the ATA/ATAPI interface for the command and
status stages. However, during the data stage, the sector FIFO and ATA/ATAPI controller along with the
DMA engine are used to process the transfer when the firmware sets the MAP_SECF bit in either the
IEPCNFG_n or OEPCNFG_n register and sets the START_ATAPI bit in the ATPIFCNFG1 register. The
firmware is not required to be involved in the lengthy data stage transfer.
• Fully automatic mode—In this mode, the MCU must handle only the status stage and the partial
command stage. During the command stage, the firmware is not required to send the CBWCB to the drive
manually. Instead, it must only fill up the correct contents required for the current CBW into the Task_File
registers of the group 0 registers. Once the firmware finishes this task, the only thing it is required to do
is set the AUTO_CMD and START_ATAPI bits in the ATPIFCNFG1 register. The ATA/ATAPI controller of
the TUSB6250 then performs the command writes to the ATA/ATAPI drive in the sequence required by
the ATA/ATAPI-5 specification, followed by the data transfer, if any. The MAP_SECF bit must be set in
either the IEPCNFG_n or OEPCNFG_n register in order to use the sector FIFO for the automatic data
transfer in the data stage. When the ATA/ATAPI controller finishes the transfer of the data stage, it triggers
the MCU with an ATA/ATAPI interrupt (vector value of 0x48) with the command completion information
provided in some of the group-2 registers. The hardware also clears the MAP_SECF bit so that the
following status stage and command stage of the next CBW can use the 4K-byte EDB. The firmware then
starts the status stage task to prepare the information required in the CSW to be sent back to the host.
This mode has the highest data transfer throughput among all three modes due to the minimum MCU
involvement.