Datasheet

ATA/ATAPI Interface Port
11−5
SLLS535E − March 2008 TUSB6250
PWR100
Pulled High by
External Pullup
Resistor
PWR500
Signal-Connect
to the USB Host
TUSB6250 Configured
by the USB Host
RST_ATA
t
0
Pulled Low by
Internal Pulldown
Resistor
Driven Low by
TUSB6250 Under
Firmware Control
Figure 11−3. ATA/ATAPI Bus Power-Up and Reset Sequence
Note that the PWR500
function showed in the Figure 11−3 is not implemented in the TUSB6250 hardware.
The option of whether to implement this functionality in the firmware as described is up to the end-product
developer. The detailed ATA/ATAPI bus behavior is described as follows for reference. Figure 11−3 assumes
the power-up reset to the TUSB6250 is finished and the controller is in the boot sequence under the control
of boot code at the beginning, which is marked as the time t
0
as shown:
• After power-up reset, the whole ATA/ATAPI interface of the TUSB6250 is disabled with all output buffers
turned off. Internal 200-µA pulldown resistors are enabled on all signals of the ATA/ATAPI bus to avoid
bus floating. As shown in Figure 11−3, the output buffer on the RST_ATA
signal is also turned off with the
internal pulldown resistor enabled.
• Both the PWR100
and PWR500 pins are open-drain outputs without internal pullup or pulldown resistors.
Their open-drain buffers are turned off during power-up reset. It is the developer’s responsibility to have
external pullup resistors to pull these two signals up during power up.
• Whenever VBUS is detected from the upstream USB bus, the boot code drives PWR100
low to indicate
that the controller is in the enumeration stage and allowed to consume 100 mA from the VBUS. This can
also serve as an alert signal to let the ATA/ATAPI device connected to the TUSB6250 ATA/ATAPI interface
prepare for the upcoming ATA/ATAPI power-up reset sequencing.
• When the TUSB6250 is fully configured by the upstream USB host, the end-product-specific application
firmware could choose to drive the PWR500
signal to low, which could be used to indicate that the
complete end product is allowed to draw 500 mA for a bus-powered application. This signal, if
implemented in firmware, can also act as a power-control signal to turn on the ATA/ATAPI drive.
• Once the TUSB6250 is fully configured and the application firmware is fully loaded, the boot code hands
over the control to the application firmware, which reconfigures all GPIOs and pullup and pulldown
resistors to meet the application requirement. When the firmware is ready, it drives the RST_ATA
pin low
by setting the HARD_RST bit in the ATPIFCNFG1 register. The firmware then enables the ATA/ATAPI bus
by clearing the ATP_DIS bit in the CMNDLNGTH register to start the ATA/ATAPI power-up reset
sequencing. The firmware then clears the HARD_RST bit tode-assert RST_ATA
when the ATA/ATAPI
reset duration time is met.
• In case the boot code fails to detect the VBUS during boot time, it leaves the PWR100
alone (without
driving it). The firmware, once it has taken over, must perform the power sequencing to the ATAPI drive
by asserting these two power-control signals. This applies to both the bus-powered application and the
self-powered application.