Datasheet

ATA/ATAPI Interface Port
11−3
SLLS535E − March 2008 TUSB6250
The sector FIFO can be accessed by the UBM, ATA/ATAPI controller, and the MCU, where the MCU can only
be indirectly accessed by going through the ATA/ATAPI CSR and the sector FIFO controller. The UBM access
has the highest priority, the ATA/ATAPI controller has the middle level access priority, and the MCU access
has the lowest priority.
11.1.3 ATA/ATAPI CSR Registers
The ATA/ATAPI CSR register block contains all the ATA/ATAPI control and status registers, which are
categorized into three register groups based on their function.
• ATA/ATAPI group 0 registers—This group consists of 16 Task_File registers, which are normally used
to pass commands along with the related parameters to the ATA/ATAPI drives in auto-command modes
that are described in Section 11.3, TUSB6250 ATA/ATAPI Controller Transfer Modes.
• ATA/ATAPI group 1 registers—The 16 registers of this group normally are used to configure the
ATA/ATAPI interface (for example, transfer mode, speed and timing, etc.) and set up the parameters
needed for the data transfer to be performed (for example, transfer byte-count, command length, block
sector count, etc.).
• ATA/ATAPI group 2 registers—The 26 registers of this group normally are used to check the status of
the drive and data transfer through the ATA/ATAPI interrupt registers. The group also includes the
registers to enable the MCU access to the sector FIFO. There are some registers that allow the firmware
to handle all 13 cases of the bulk-only transfer protocol specification when there is any error condition on
the ATA/ATAPI drive side.
As described previously, the MCU can access the sector FIFO only indirectly by using its address and data
registers in the ATA/ATAPI group 2 registers (MCU data byte_n registers and the MCU access address
low-/high-byte registers).