Datasheet

ATA/ATAPI Interface Port
11−2
SLLS535E − March 2008TUSB6250
11.1 TUSB6250 ATA Controller Architecture Overview
The TUSB6250 ATA/ATAPI controller contains three state machines, the ATA/ATAPI CSR registers, and the
sector FIFO controller, as illustrated in Figure 11−2. The sector FIFO controller is the high-performance DMA
engine discussed in the previous section.
Ultra DMA
State Machine
PIO-DMA
State Machine
Transaction
State Machine
Sector FIFO
RAM
TUSB6250 ATA/ATAPI Controller
Sector FIFO
Controller
ATA/ATAPI
CSR Registers
ATA/ATAPI
Port
MCU
Figure 11−2. TUSB6250 ATA/ATAPI Controller Block Diagram
11.1.1 ATA/ATAPI Controller State Machine
The following state machines are responsible for command and data transfer between the ATA/ATAPI
interface port and the TUSB6250 internal logic.
• Transaction state machine—The transaction state machine handles command level transactions. It
also controls the PIO-DMA state machine and the ultra DMA state machine to perform actual data transfer
between the TUSB6250 internal logic and the ATA/ATAPI interface port.
• PIO-DMA state machine—The PIO-DMA state machine handles PIO transfers and multiword DMA
transfers.
• Ultra DMA state machine—The ultra DMA state machine handles ultra DMA transfers.
11.1.2 Sector FIFO Controller
As described in Section 6.1, MCU Memory Map, the sector FIFO RAM is used as the data buffer for the data
being transferred between the TUSB6250 ATA/ATAPI interface and the USB interface in the automatic
data-transfer mode. The name sector FIFO implies it is derived from the data buffer for the sector data of an
ATA hard-disk drive, although the sector FIFO of the TUSB6250 can actually be used for either ATA or ATAPI
data buffering in the automatic data transfer mode. The TUSB6250 features a unique size-configurable sector
FIFO to allow efficient code and data space usage. The sector FIFO size can be partitioned as 8K bytes,
24K bytes, or 32K bytes.