Datasheet

I
2
C Interface Controller
10−8
SLLS535E − April 2008TUSB6250
10.7 I
2
C EEPROM Head Block
To fully use the maximum speed of the variety of I
2
C EEPROMs on the market, the I
2
C interface controller
in the TUSB6250, along with boot code and firmware, features a special mechanism to detect the speed
supported by the I
2
C EEPROM connected to its I
2
C port. In order that the auto-detect mechanism works
correctly, it is required that any I
2
C EEPROM connected to the I
2
C port with valid data stored, must have a
fixed 2-byte signature at address 0 of the I
2
C EEPROM.
Table 10−1. I
2
C EEPROM Signature in Descriptor Block
I
2
C EEPROM ADDRESS REQUIRED SIGNATURE IN I
2
C EEPROM
Byte 0 (hex) 0x50
Byte 1 (hex) 0x62
Byte 2 (hex) Starting I
2
C EEPROM header/descriptor block
… …
NOTE: For detailed information regarding the I
2
C EEPROM header/descriptor block, see
the TUSB6250 Boot Code application note (SLLA126).
During the power-up boot-up sequence, the boot code uses the following sequences to determine whether
the I
2
C EEPROM connected has any valid data.
1. Reads byte 0 and byte 1 in the I
2
C EEPROM with 100 Kbits/sec speed (based on the default reset value
of SP bit in the I2CSCR register) to see whether the connected I
2
C EEPROM returns a valid signature
0x6250.
a. If a valid signature is returned, the boot code concludes that the I
2
C EEPROM contains valid data.
b. The boot code then operates according to the boot sequence defined in the TUSB6250 boot code
document.
2. If the foregoing read does not return the valid signature, the boot code considers that either the I
2
C
EEPROM is blank or there is no I
2
C EEPROM connected at the TUSB6250 I
2
C port.