Datasheet

I
2
C Interface Controller
10−2
SLLS535E − April 2008TUSB6250
10.1 I
2
C Registers
10.1.1 IECSCR: I
2
C Status and Control Register (XDATA at F0B0)
The IECSCR register contains the I
2
C EERPOM speed, error condition indication, and provides status
information for the I
2
C data registers. It is also used to control the stop condition for read and write operation.
In addition, it provides transmitter and receiver handshake signals.
76543210
RXF RSV ERR RSV SP TXE RSV STOP
R/O R/O R/C R/O R/W R/O R/O R/W
BIT
NAME RESET FUNCTION
0 STOP 0 Stop read or write condition generation. By setting or clearing this bit, the MCU can control the I
2
C
interface controller to generate a stop condition after writing data to or reading data from I
2
C EEPROM.
STOP = 0 Stop condition is not generated for:
 Writes when data from the I2CDOUT register is shifted out to an external I
2
C device.
 Reads when data from the SDA line is shifted into the I2CDIN register.
STOP = 1 Stop condition is generated for:
 Writes when data from the I2CDOUT register is shifted out to an external I
2
C device.
 Reads when data from the SDA line is shifted into the I2CDIN register.
1 RSV 0 Reserved = 0
2 TXE 1 I
2
C transmitter empty. This bit, when set, indicates that the MCU can write data to the I2CDOUT register.
TXE = 0 Transmitter is full. This bit is cleared when the MCU writes a byte to the I2CDOUT register.
TXE = 1 Transmitter is empty. The I
2
C controller sets this bit when the contents of the I2CDOUT are
copied into the SDA shift register.
3 SP 0 I
2
C EEPROM speed
SP = 0 I
2
C speed is 100 kbps.
SP = 1 I
2
C speed is 400 kbps.
4 RSV 0 Reserved = 0
5 ERR 0 Bus error condition. This bit is set by the hardware when the device does not respond. It is cleared by the
MCU. This bit is cleared when the MCU writes a 1 to this bit. Writing a 0 to this bit has no effect.
ERR = 0 No bus error
ERR = 1 Bus error condition has been detected
6 RSV 0 Reserved = 0
7 RXF 0 I
2
C receiver full. This bit indicates that the receiver contains new data.
RXF = 0 Receiver is empty. This bit is cleared when the MCU reads the I2CDIN register.
RXF = 1 Receiver contains new data. This bit is set by the I
2
C interface controller when the received serial
data has been loaded into the I2CDIN register.
10.1.2 I2CADR: I
2
C Device Address Register (XDATA at F0B1)
The I2CADR register holds the I
2
C device address and the read/write command bit.
76543210
A6 A5 A4 A3 A2 A1 A0 R/W
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
0 R/W 0 Read/write command bit
R/W
= 0 Write operation
R/W
= 1 Read operation
7−1 A[6:0] 00h Seven address bits for I
2
C device addressing