Datasheet

I
2
C Interface Controller
10−1
SLLS535E − April 2008 TUSB6250
10 I
2
C Interface Controller
The master-only I
2
C interface controller in the TUSB6250 provides a simple two-wire serial interface for the
MCU to communicate with the external EEPROM. It supports single-byte or multiple-byte read and write
operations. The I
2
C interface controller can be programmed to operate at either 100 Kbit/sec or 400 Kbit/sec.
In addition, the protocol supports 8-bit or 16-bit addressing for accessing the I
2
C slave device memory
locations. The embedded I
2
C interface controller however, does not support a multimaster bus environment
(no bus arbitration).
The main function of the I
2
C interface controller is to provide the data path for the descriptor and application
firmware to be downloaded from the external I
2
C EEPROM to the internal on-chip code RAM. The TUSB6250
only supports widely available 3.3-V I
2
C serial EEPROMs. The two interface signals provided by the I
2
C
interface controller are the serial clock signal (SCL) and the serial data signal (SDA). The SCL signal is output
only open-drain. The SDA signal is a bidirectional signal that uses an open-drain output to allow the TUSB6250
to be wire-ORed with other I
2
C slave devices that use open-drain or open-collector outputs. Internal weak
100-µA pullup resistors are built into both the SCL and SDA pins. The pullup resistors are always activated
after a power-up reset.
All read and write data transfers on the I
2
C serial bus are initiated by the master device. The master device
is also responsible for generating the clock signal used for all data transfers. The data is transferred on the
bus serially, one bit at a time. However, the protocol requires that the address and data be transferred in byte
(8 bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus
is acknowledged by the receiving device with an acknowledge bit.
Each transfer operation begins with the master device driving a start condition on the bus and ends with the
master device driving a stop condition on the bus. During I
2
C serial data transmission, the SDA line must be
stable while the SCL signal is high, which also means that the SDA signal can only change state while the SCL
signal is low.
• The start condition of the I
2
C serial transmission is defined as a high-to-low transition of the SDA signal
while the SCL signal is high.
• The stop condition is defined as a low-to-high transition of the SDA signal, while the SCL signal is high.
• The acknowledge is defined as a stable low of the SDA line driven by the receiver after each byte has been
received, except when the receiver is unable to receive or transmit or after the master-receiver receives
the last byte. The transmitter must release the SDA line during the acknowledge clock phase.
For the detailed behavior and protocol of the I
2
C data transmission, see the industry standard I
2
C bus
specification.
Based on the I
2
C convention, there are normally two types of I
2
C devices:
• Category II device: For those I
2
C EEPROMs with a size less than 4K bytes (up to 11 EEPROM address
bits could be used).
• Category III device: For those I
2
C EEPROMs with a size equal to or larger than 4K bytes (up to 16
EEPROM address bits could be used).
For application firmware with sizes equal to or larger than 4K bytes, the TUSB6250 boot code requires that
the application firmware be stored in an external I
2
C EEPROM, with its device address A0 pin (the least
significant device address input pin or chip select-0 as referred to in some I
2
C EEPROM’s data manual) tied
to 1. This indicates to the boot code that the I
2
C EEPROM connected to the I
2
C interface of the TUSB6250
is a category III I
2
C EEPROM.
Developers should not confuse the I
2
C device address with the I
2
C EEPROM address. The I
2
C device address
is the address for a particular I
2
C EEPROM device, which should be set up in the I2CADR register and sent
to the I
2
C EEPROM. The I
2
C EEPROM address is the I
2
C internal EEPROM memory cell address, which
should be set up in the I2CDOUT register and sent to the I
2
C EEPROM during data phase communication.