Datasheet

Miscellaneous and GPIO Configuration Registers
9−5
SLLS535E − April 2008 TUSB6250
9.5 PUPDPWDN_P3: GPIO Pullup and Pulldown Resistor Power-Down Register for
Port 3 (XDATA at F08D)
The PUPDWDN_P3 register allows the MCU to enable/disable the internal pullup and pulldown resistors that
are connected to the port-3 GPIO pins. To choose the desired pullup or pulldown resistor for a particular pin,
the MCU must ensure that the correct setup is done in the PUPDSLCT_P3 register before enabling the
corresponding bit in this register.
PUPDOFF[N] means the pullup/pulldown resistors disable or power down for the P3.N pin.
76543210
PUPDOFF7 PUPDOFF6 PUPDOFF5 PUPDOFF4 PUPDOFF3 PUPDOFF2 PUOFF1 PUOFF0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
0 PUOFF0 0 Port-3 GPIO pin P3.0 pullup resistor configuration by the MCU.
 If the MCU sets this bit to 1, the pullup resistor is disconnected from the P3.0 pin.
 If the MCU clears this bit to 0, the pullup resistor is connected to the P3.0 pin.
The power-up default is to enable the pullup resistor on the P3.0 pin.
1 PUOFF1 0 Port-3 GPIO pin P3.1 pullup resistor configuration by the MCU.
 If the MCU sets this bit to 1, the pullup resistor is disconnected from the P3.1 pin.
 If the MCU clears this bit to 0, the pullup resistor is connected to the P3.1 pin.
The power-up default is to enable the pullup resistor on the P3.1 pin.
7−2 PUPDOFF[N]
(N = 2 to 7)
000000 Port-3 GPIO pin P3.2 – P3.7 pullup and pulldown resistor power down configuration by the MCU.
 If the MCU sets any of these bits to 1, both the pullup and pulldown resistors are disabled on
the corresponding pin P3.2–P3.7.
 If the MCU clears any of these bits to 0, either the pullup or the pulldown resistor is enabled
for the corresponding pin P3.2–P3.7, with the selection controlled by the corresponding bit
of the PUPDSLCT_P3 register.
The power-up default is to enable the pullup/pulldown resistors for pins P3.2–P3.7.