Datasheet

Miscellaneous and GPIO Configuration Registers
9−2
SLLS535E − April 2008TUSB6250
• Following the standard 8051 convention, both port 2 and port 3 are bit addressable, which implies that
within the same GPIO port, some pins can be configured as inputs and others as outputs.
9.1 MODECNFG: Mode Configuration Register (XDATA at F088)
The MODECNFG register contains several parameters the MCU can use to configure the code and data RAM
partition, polarity of the INTRQ pin, and code RAM write access enable.
The MODECNFG register is cleared by a power-up reset or a WDT reset only. A USB reset cannot clear the
MODECNFG register.
76543210
RSV RSV RSV RSV INTRQPOLR RAMPARTN1 RAMPARTN0 RAMWR_DIS
R/O R/O R/O R/O R/W R/W R/W R/W
BIT NAME RESET FUNCTION
0 RAMWR_DIS 0
Disables/enables the MCU write to the complete space of the code RAM with the space defined
by RAMPARTN[1:0] bits.
RAMWR_DIS = 0 Allows the MCU write to the code RAM.
RAMWR_DIS = 1 Disables the MCU write to the code RAM.
2−1 RAMPARTN
[1:0]
00 Code/data RAM partition setting bits. These bits are used by the MCU to change the default
partition of the 40K bytes of RAM to the other two supported code/sector FIFO memory
configurations. The TUSB6250 allows the maximum code size to be 32K bytes.
RAMPARTN[1:0] = 00 40K bytes of RAM is partitioned to be 32K bytes code and 8K bytes sector
FIFO (default).
RAMPARTN[1:0] = 01 40K bytes of RAM is partitioned to be 16K bytes code and 24K bytes
sector FIFO.
RAMPARTN[1:0] = 10 40K bytes of RAM is partitioned to be 8K bytes code and 32K bytes sector
FIFO.
RAMPARTN[1:0] = 11 Reserved
3 INTRQPOLR 0 TUSB6250 INTRQ pin polarity configuration by the MCU.
INTRQPOLR = 0 INTRQ is active-high (default setting as defined in the ATA/ATAPI
specification).
INTRQPOLR = 1 INTRQ is active-low.
7−4 RSV 0h Reserved