Datasheet

Miscellaneous and GPIO Configuration Registers
9−1
SLLS535E − April 2008 TUSB6250
9 Miscellaneous and GPIO Configuration Registers
The TUSB6250 offers up to 13 GPIOs and three additional general-purpose open-drain outputs that can be
used for an end-product-specific function. All the GPIOs and general-purpose open-drain outputs are mapped
to port 2 and port 3 of the embedded MCU. Table 9−1 illustrates the TUSB6250 GPIO port mapping for the
embedded MCU and some recommended usage.
Table 9−1. TUSB6250 Controller MCU GPIO Port Mapping
EMBEDDED MCU
PORT 3 AND PORT 2
GPIO
TUSB6250
PIN MAPPING
RECOMMENDED PIN USAGE/FUNCTION
Port 3[0] P3.0/SIN SIN (serial in of the 8051 built-in serial port) or GPIO
Port 3[1] P3.1/SOUT SOUT (serial out of the 8051 built-in serial port) or GPIO
Port 3[2] P3.2/CD1 Remote-wakeup-capable GPIO can be used as a compact flash card insertion detect signal.
Port 3[3] P3.3/CD2 Remote-wakeup-capable GPIO can be used as a compact flash card insertion detect signal.
Port 3[4] P3.4 Remote-wakeup-capable GPIO
Port 3[5] P3.5 Remote-wakeup-capable GPIO
Port 3[6] P3.6 GPIO or ATA/ATAPI passed diagnostic/cable identifier (not implemented in hardware)
Port 3[7] P3.7 GPIO or ATA/ATAPI device active/device-1 present (not implemented in hardware)
Port 2[0] P2.0 GPIO
Port 2[1] P2.1/PWR100 General-purpose open-drain output for power-control purposes
Port 2[2] P2.2/PWR500 General-purpose open-drain output for power-control purposes (not implemented in
hardware)
Port 2[3] P2.3 General-purpose open-drain output
Port 2[4] P2.4 GPIO
Port 2[5] P2.5 GPIO
Port 2[6] P2.6 GPIO
Port 2[7] P2.7 GPIO
The GPIO pins of this controller have integrated pullup and/or pulldown resistors. As described in the following
sections, these pullup and/or pulldown resistors can be easily configured by the MCU using the related pullup
and pulldown configuration registers to meet the need for a broad range of applications.
The pullup resistor, if enabled, is connected between the GPIO pin and the DVDD power supply. The pulldown
resistor, if enabled, is connected between the GPIO pin and ground.
There are some important notes regarding the port-2 and port-3 GPIOs of this controller:
• All the port-2 GPIO pins, except P2.7, are 5-V fail-safe. P2.7 is a standard 3.3-V LVCMOS GPIO with only
a pullup resistor integrated internally.
• All the port-3 GPIO pins, except P3.0 and P3.1, are 5-V fail-safe. P3.0 and P3.1 are standard 3.3-V
LVCMOS GPIOs with only a pullup resistor integrated internally.
• Developers must pay special attention to a standard 8051 microcontroller feature, that is, the output buffer
of a GPIO pin only actively drives one MCU clock cycle for a 0-to-1 transition on the data bit of any GPIO
port (internally connected to the input of the GPIO output buffer). The GPIO pin then floats to allow the
weak pullup to maintain the logic-1 state.
• Based on the above standard 8051 behavior, the firmware and board level developers must ensure that
no pulldown resistor is enabled, either internal or external on the GPIO pin, if its output buffer is used to
output a logic 1 state, otherwise, the pulldown discharges the logic-1 value on the GPIO pin. In other
words, the pullup must be enabled by the firmware whenever the output buffer is used to output a logic-1
state for any GPIO.
• If a GPIO is configured as input-only, the firmware can select either a pullup or pulldown resistor to be
enabled for that GPIO pin.