Datasheet

8−10
SLLS535E − April 2008TUSB6250
8.6 USBFCL: USB Frame Counter Low-Byte Register (XDATA at F00B)
The USBFCL register contains the read-only USB frame counter low-byte value of the 11-bit frame number
value received from the USB host in the start-of-frame packet. The frame number bit values are updated by
the hardware for each USB frame with the frame number field value received in the USB start-of-frame packet.
The frame number can be used as a time stamp by the USB function. If the frame number of the TUSB6250
is not locked to the USB host frame timer, then the frame number is incremented from the previous value when
a pseudo start-of-frame occurs.
The USBFCL register is cleared by a power-up reset or a WDT reset. A USB reset cannot clear the USBFCL
register.
76543210
FRAMNUM7 FRAMNUM6 FRAMNUM5 FRAMNUM4 FRAMNUM3 FRAMNUM2 FRAMNUM1 FRAMNUM0
R/O R/O R/O R/O R/O R/O R/O R/O
BIT
NAME RESET FUNCTION
7−0 FRAMNUM[7:0] 00h These bits indicate the frame number lower-order 8-bit value.
8.7 USBFCH: USB Frame Counter High-Byte Register (XDATA at F00C)
The FRAMNUM[10:8] bits of the USBFCH register contain the read-only USB frame counter high-byte value
of the 11-bit frame number value received from the USB host in the start-of-frame packet. The UFRMNUM[2:0]
bits contain the read-only micro frame number.
The USBFCH register is cleared by a power-up reset or a WDT reset. A USB reset cannot clear the USBFCH
register.
76543 2 10
RSV RSV UFRAMNUM2 UFRAMNUM1 UFRAMNUM0 FRAMNUM10 FRAMNUM9 FRAMNUM8
R/O R/O R/O R/O R/O R/O R/O R/O
BIT
NAME RESET FUNCTION
2−0 FRAMNUM[10:8] 000 These bits indicate the frame number higher-order 3-bit value.
5−3 UFRAMNUM[2:0] 000 These three bits indicate the microframe number.
7−6 RSV 00 Reserved. The application firmware must ensure these two bits are set to 00 during normal
operation.
8.8 USBWKUP: USB Wake-Up Reason Register (XDATA at F00D)
The USBWKUP register indicates the USB wakeup event reason (source) from the embedded MCU’s port-3
GPIO pins and VBUS pin.
All four status-change bits (P34CHG, P35CHG, VBUSCHG, and CDCHG) in the USBWKUP register are set
individually by the hardware when their corresponding enable bit is set in the MCUCNFG register (at ESFR
FCh), with the exception that VBUSCHG is always enabled. They can be cleared by the MCU writing a 1 to
the proper bit location (writing a 0 has no effect). In addition, the OR-result of these four status-change bits,
when set, generates the WAKCLK interrupt if the interrupt is enabled in the USBMSK register (R/C notation
indicates read and set-to-clear only by the MCU).
Any status-change bit, when set, indicates there is a status-change event that occurred since the last time the
MCU cleared the same status-change bit. Below are important notes regarding the consecutive status-change
events that occur before the MCU services and clears the current WAKCLK interrupt, assuming the related
status-change event is enabled in the MCUCNFG register.
• As described in Section 8.3.2, WAKCLK Interrupt and Remote Wakeup, regardless if the new
status-change event occurring is the same as the one that already occurred, consecutive status-change