Datasheet

Contents
vi
SLLS535E − April 2008TUSB6250
Section Page
11.5.10 TRANSBCNT3: USB or ATA/ATAPI Transfer Byte Count Register 3
(XDATA at F0D9) 11−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5.11 CMNDLNGTH: Command Length Register (XDATA at F0DA) 11−15. . . . . . . . . . . . . . . . . . .
11.5.12 PIOSPAS: PIO Transfer Speed (Assertion Time) Register (XDATA at F0DC) 11−15. . . . . .
11.5.13 PIOSPRC: PIO Transfer Speed (Recovery Time) Register (XDATA at F0DD) 11−16. . . . . .
11.5.14 DMASPAS: DMA Transfer Speed (Assertion Time) Register (XDATA at F0DE) 11−16. . . .
11.5.15 DMASPRC: DMA Transfer Speed (Recovery Time) Register (XDATA at F0DF) 11−16. . . .
11.5.16 Data Transfer Mode and Timing Reference Chart 11−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6 ATA/ATAPI Group 2 Registers 11−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6.1 MCUBYTE0: MCU Data Byte_0 Register (XDATA at F0E0) 11−20. . . . . . . . . . . . . . . . . . . . .
11.6.2 MCUBYTE1: MCU Data Byte_1 Register (XDATA at F0E1) 11−20. . . . . . . . . . . . . . . . . . . . .
11.6.3 MCUBYTE2: MCU Data Byte_2 Register (XDATA at F0E2) 11−20. . . . . . . . . . . . . . . . . . . . .
11.6.4 MCUBYTE3: MCU Data Byte_3 Register (XDATA at F0E3) 11−20. . . . . . . . . . . . . . . . . . . . .
11.6.5 MCUACSL: MCU Access Address Low-Byte Register (XDATA at F0E4 11−21. . . . . . . . . . .
11.6.6 MCUACSH: MCU Access Address High-Byte Register (XDATA at F0E5) 11−21. . . . . . . . .
11.6.7 ATPINTRPT0: ATA/ATAPI Interrupt Register 0 and ATPINTMSK0: ATA/ATAPI
Interrupt Mask Register 0 (XDATA at F0E6, F0E7) 11−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6.8 ATPINTRPT1: ATA/ATAPI Interrupt Register 1 and ATPINTMSK1: ATA/ATAPI
Interrupt Mask Register 1 (XDATA at F0E8, F0E9) 11−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6.9 ATPSTATUS: ATA/ATAPI Interface Status Register (XDATA at F0EA) 11−23. . . . . . . . . . . .
11.6.10 SECWRPTL: Sector FIFO Write Pointer Low-Byte Register (XDATA at F0EB) 11−24. . . . .
11.6.11 SECWRPTH: Sector FIFO Write Pointer High-Byte Register (XDATA at F0EC) 11−25. . . .
11.6.12 WRPTBKUPL: Sector FIFO Write Pointer Backup Low-Byte Register
(XDATA at F0ED) 11−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6.13 WRPTBKUPH: Sector FIFO Write Pointer Backup High-Byte Register
(XDATA at F0EE) 11−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6.14 SECRDPTL: Sector FIFO Read Pointer Low-Byte Register (XDATA at F0EF 11−25. . . . . .
11.6.15 SECRDPTH: Sector FIFO Read Pointer High-Byte Register (XDATA at F0F0 11−26. . . . .
11.6.16 RDPTBKUPL: Sector FIFO Read Pointer Backup Low-Byte Register
(XDATA at F0F1 11−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6.17 RDPTBKUPH: Sector FIFO Read Pointer Backup High-Byte Register
(XDATA at F0F2 11−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6.18 ULRCVEXCNT: Ultrareceive Extra Word Count Register (XDATA at F0F9) 11−27. . . . . . . .
12 Electrical Specifications 12−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 Absolute Maximum Ratings 12−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Recommended Operating Conditions 12−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 Electrical Characteristics for the Digital Core, T
A
= 25°C, V
CC
= 3.3 V ±5%, V
SS
= 0 V 12−2. . . . . . .
12.4 Controller Input Supply Current, T
A
= 25°C, V
CC
= 3.3 V ±5%, V
SS
= 0 V 12−2. . . . . . . . . . . . . . . . . . .
12.5 Timing for 5-V Failsafe TTL Compatible LVCMOS I/O Buffer Used in the TUSB6250
ATA/ATAPI Interface 12−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6 Electrical Characteristics for the Integrated USB 2.0 Transceiver, T
A
= 25°C,
V
CC
= 3.3 V ±5%, V
SS
= 0 V 12−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 Application Information 13−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1 Crystal Selection and Reference Circuitry 13−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 Reset Timing Reference 13−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3 General ATA/ATAPI Device Application Information 13−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.1 ATA/ATAPI Connector Pin Diagram 13−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.2 Special Note About Shaded Signals 13−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.3 Special Note About Pullup and Pulldown Resistors for ATA/ATAPI Signals 13−5. . . . . . . . .
13.3.4 Series Termination Required for Ultra DMA Operation 13−5. . . . . . . . . . . . . . . . . . . . . . . . . . .