Datasheet

8−5
SLLS535E − April 2008 TUSB6250
For the TUSB6250, the timing to enter the USB suspend is controlled by the application firmware running on
the embedded MCU. This flexibility allows the firmware to delay the time to go into suspend when the MCU
is currently busy on some tasks that must be finished before the suspend.
Because the firmware controls the time to enter the suspend, in order to be compliant with USB 2.0
specification, it is firmware responsibility to ensure that it clears the SUSPR interrupt status bit before 10 ms
expires.
The normal procedure during the bus idle and suspend condition is described as follows:
1. The TUSB6250 hardware detects 3-ms bus idle.
2. If the current USB bus connection is full speed, the TUSB6250 hardware sets the SUSPR bit in the
USBSTA register and generates an SUSPR (function suspend request) interrupt to the MCU.
If the current USB bus connection is high-speed, the TUSB6250 hardware reverts back to a full-speed
connection within 0.125 ms, then sets the SUSPR bit and generates the SUSPR interrupt.
3. The firmware can check whether there is any task that must be finished before the suspend and performs
it if desired. The firmware must ensure it grants the suspend request before 10 ms expires.
4. Once the firmware is ready to enter suspend, it clears the SUSPR bit in the USBSTA register. The
TUSB6250 hardware shuts the clock down (if LPEN = 1) and enters the suspend state.
8.3.2 WAKCLK Interrupt and Remote Wakeup
8.3.2.1 WAKCLK Interrupt Behavior
Figure 8−1 illustrates how the WAKCLK interrupt and WAKCLK status-change events are generated and
cleared. The top portion of the diagram shows how each of the WAKCLK status-change events causes the
WAKCLK bit in the USBSTA register to be set, if the WAKCLK interrupt is enabled in the USBMSK register
(for illustration purpose, WAKCLK_en = 1 in Figure 8−1 implies WAKCLK = 1 in USBMSK). The
VBUSCHG_det and the other three status-change event detection signals are generated internally by the
TUSB6250 hardware, whenever a WAKCLK status-change event occurs on the VBUS pin or the other four
remote wakeup capable port 3 GPIO pins (P3.2, P3.3, P3.4, and P3.5). These four status-change-event
detection signals, lasting one clock cycle, are ORed together to form a single cycle pulse to set the WAKCLK
bit in the USBSTA register, as long as the WAKCLK interrupt is enabled and the WAKCLK bit is not set.
Described below are important behaviors regarding the WAKCLK interrupt.
• The WAKCLK interrupt is triggered if any one of the four status-change events occurs, when the WAKCLK
bit is not yet set in USBSTA, the core clock is available, and the WAKCLK interrupt is enabled.
• The WAKCLK interrupt is shared among four different status-change events (interrupt sources). Before
the MCU clears the WAKCLK interrupt triggered by the first event, any new status-change event occurring
does not trigger a new WAKCLK interrupt. In other words, multiple status-change events only trigger one
WAKCLK interrupt before the MCU clears the existing WAKCLK residing in the interrupt queue.
• For the same reason, because the WAKCLK interrupt is shared, writing a 1 to the WAKCLK bit in the
USBSTA register clears the interrupt triggered by all the WAKCLK interrupt sources (status-change
events), although the individual status-change event bits are still kept in the USBWKUP register. In other
words, clearing one WAKCLK interrupt is like clearing all WAKCLK interrupts triggered by multiple
status-change events; although physically there is only one WAKCLK interrupt residing in the interrupt
queue.
• To avoid potential interrupt loss caused by mistaken writes, firmware developers must follow the
recommended procedure when servicing the WAKCLK interrupt. In summary, the WAKCLK bit must be
cleared before any status-change bit is cleared in the USBWKUP register.
− Once triggered by the WAKCLK interrupt, the firmware first must write a 1 to the WAKCLK bit in the
USBSTA register to clear the physical interrupt;