Datasheet

8−4
SLLS535E − April 2008TUSB6250
8.3 USBSTA: USB Status Register (XDATA at F008)
Each bit in the USBSTA register can generate an interrupt if its corresponding mask bit is set in the USBMSK
register. The related interrupt is cleared when the corresponding status bit is cleared by the MCU except the
WAKCLK interrupt. All bits in this register are set by the hardware and can only be cleared by the MCU by
writing a 1 to the proper bit location (writing a 0 has no effect).
The USBSTA register (excluding the RSTR bit) is cleared by a power-up reset or a WDT reset. It can also be
cleared by a USB reset, when the function reset connection bit in the USBCTL register is set (FRSTE = 1).
The RSTR bit of the USBSTA register can only be cleared by a power-up reset or a WDT reset. A USB reset
sets this bit to 1.
76543210
RSV RSV RSTR SUSPR RESUR WAKCLK SETUP STPOW
R/O R/O R/C R/C R/C R/C R/C R/C
BIT
NAME RESET FUNCTION
0 STPOW 0 SETUP overwrite bit. Set by the hardware when the setup packet is received, while there is already
a packet in the setup buffer. The MCU clears this bit by writing a 1 (writing 0 has no effect).
1 SETUP 0 SETUP transaction received bit. As long as SETUP is 1, IN and OUT on endpoint-0 are NAKed,
regardless of their real NAK bits value. The MCU clears this bit by writing a 1 (writing 0 has no effect).
2 WAKCLK 0 Wakeup clock request bit. When WAKCLK interrupt is enabled, this bit is set in response to the status
change on any of these pins: VBUS, P3.4, P3.5, CD1
, or CD2. The interrupt generated due to this bit
in turn wakes up the core clock if it has been shut down during suspend, when the remote wakeup is
enabled.
WAKCLK = 0 No wakeup clock event (status change on the five GPIO pins) is detected since the last
time the MCU clears the related status-change bit in USBWKUP.
WAKCLK = 1 Wakeup clock event (any status change on the five GPIO pins) is detected since the
last time the MCU clears the related status-change bit in USBWKUP.
3 RESUR 0 Function resume request bit. The MCU clears this bit by writing a 1 (writing 0 has no effect).
RESUR = 0 No function resume is detected.
RESUR = 1 Function resume is detected.
4 SUSPR 0 Function suspended request bit. This bit is set in response to a global or selective suspend condition.
The MCU clears this bit by writing a 1 (writing 0 has no effect).
SUSPR = 0 No function suspend is detected.
SUSPR = 1 Function suspend is detected.
5 RSTR 0 Function reset request bit. This bit is set in response to the host initiating a port reset to the TUSB6250.
The USB function reset is the condition to set this bit, not clear this bit. The MCU clears this bit by writing
a 1 (writing 0 has no effect).
RSTR = 0 No function reset is detected.
RSTR = 1 Function reset is detected.
6−7 RSV 00 Reserved = 0
8.3.1 USB Suspend
The USB 2.0 specification requires that all USB devices must support the suspend state. The USB devices
begin the transition to the suspend state after they see a constant idle state on their upstream facing bus lines
for more than 3 ms. The device must actually be suspended, drawing only suspend current from the bus after
no more than 10 ms of bus inactivity on its port. The specification also requires that a device with remote
wakeup capability may not generate resume signaling, unless the bus has been continuously in the idle state
for 5 ms.
In other words, the specification allows all USB devices to enter suspend at any time between 3 ms to 10 ms
after bus idle. For USB high-speed capable devices, because there is an additional 0.125-ms revert-wait time
from high-speed to full-speed after 3-ms high-speed bus idle, the actual time to enter suspend is between
3.125 ms and 10 ms.