Datasheet

8−1
SLLS535E − April 2008 TUSB6250
8 USB Function and Registers
The MCU and firmware or boot code configure the USB function characteristics of the TUSB6250 by
configuring and updating the memory-mapped registers (located in XDATA space) described in this chapter.
8.1 USBCTL: USB Control Register (XDATA at F006)
The USBCTL register is cleared by a power up or a WDT reset. A USB reset cannot reset the USBCTL register.
76543210
CONT LPEN RWUPEN FRSTE HSTM2 HSTM1 HSTM0 DIR
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
0 DIR 0 USB (control) transfer direction. As a response to a setup packet, the MCU decodes the request and
sets/clears this bit to reflect the data transfer direction. This bit is used in the control transfer only.
DIR = 0 USB data OUT transaction
DIR = 1 USB data IN transaction
3−1 HSTM 000 USB 2.0 high-speed test mode and forced full speed.
HSTM = 000 Normal operation (the USB speed is determined by the bus connection)
HSTM = 001 Test mode test_SE0_NAK
HSTM = 010 Test mode test_J
HSTM = 011 Test mode test_K
HSTM = 100 Test mode test_packet
HSTM = 101 Normal operation (force USB full-speed connection by the MCU). A corresponding bit
in the I
2
C EEPROM header must be specified.
4 FRSTE 0 Function reset connection bit. This bit connects/disconnects the USB function reset from the MCU
reset.
FRSTE = 0 Function reset is not connected to the MCU reset.
FRSTE = 1 Function reset is connected to the MCU reset.
5 RWUPEN 0 Device remote wakeup enable.
RWUPEN = 0 Disable remote wakeup capability
RWUPEN = 1 Enable remote wakeup capability
6 LPEN 0 Low-power enable. If set to 1, the TUSB6250 is in the low-power mode during suspend and the core
clock is shut down. It is required that the self-powered application based on the TUSB6250 ensures
this bit is cleared. In other words, the TUSB6250 does not support the low-power enable feature in
the self-powered mode.
7 CONT 0 Connect/disconnect bit. This bit is used by the MCU to present a connect/disconnect condition on the
upstream port. The MCU must check the VBUS line status before setting this bit. Hardware performs
the connect to the USB bus immediately after the CONT bit is set without checking the VBUS line
status.
CONT = 0 Upstream port is disconnected.
CONT = 1 Upstream port is connected.
8.1.1 USB Enumeration
The USB enumeration is accomplished by the interaction between the host PC software, the USB host
controller and the boot code, the firmware, and the hardware of the TUSB6250. As described in Section 4.3.3,
Device Initilization, after a power-up reset, the boot code checks the firmware type in the header block of the
external I
2
C EEPROM and decides whether it must signal connection to the upstream USB host or hubs. If
the boot code is responsible to signal connect as specified, it fetches all the required USB descriptors from
the external I
2
C EEPROM and sets the CONT bit, which tells the TUSB6250 hardware to connect the external
1.5-kΩ full-speed pullup resistor to the 3.3-V power supply of the TUSB6250. This results in the DP line of the
TUSB6250 being pulled up to the logic-high level to be recognized by the upstream USB host controller or
hubs as a valid connection signal. The FRSTE bit is also set by the MCU, which enables the USB reset coming
from the USB host after signal-connection to reset the MCU and its related registers as specified in
Section 6.3, MCU Control and Status Registers (in SFR and ESFR Space).
During enumeration, the boot code or firmware identifies the TUSB6250 as a USB mass storage class-specific
device, which enables the USB host to load the appropriate driver for the TUSB6250.