Datasheet

Interrupts
7−4
SLLS535E − April 2008TUSB6250
7.2 Additional Interrupt Sources
All nonstandard 8051 interrupts (USB, I
2
C, ATA/ATAPI etc.) are ORed to generate an internal INT5. INT5 is
an active low-level interrupt (not edge triggered). A vector interrupt register is provided to identify all interrupt
sources (see Section 7.2.1, VECINT: Vector Interrupt Register (ESFR at F7), for more details). Up to 64
interrupt vectors are provided. It is the responsibility of the MCU to read the vector and dispatch the proper
interrupt routine.
The VECINT register is cleared by a power-up reset or a WDT reset. It can also be cleared by a USB reset
when the function reset connection bit in the USBCTL register is set (FRSTE = 1). All the interrupts pending
in the queue are cleared once any of the preceding reset events occurs.
7.2.1 VECINT: Vector Interrupt Register (ESFR at F7)
The VECINT register contains a vector value, which identifies the internal interrupt source that trapped to
location 0x202B. Writing any value to the VECINT register removes the vector and updates the next vector
value (if another interrupt is pending). Note that the vector value is offset; therefore, its value is in increments
of two (bit 0 is set to 0). When no interrupt is pending, the vector is set to 00h. As shown in Table 7−2, the
interrupt vector is divided into two fields: I[2:0] and G[3:0]. The I-field defines the interrupt source within a group
(on a first-come, first-serve basis) and the G-field defines the group number. Group G0 is the lowest and G15
is the highest priority.
76543210
G3 G2 G1 G0 I2 I1 I0 0
R/O R/O R/O R/O R/O R/O R/O R/O
BIT
NAME RESET FUNCTION
0 RSV 0 Reserved
3−1 I[2:0] 000 This field defines the interrupt source in a given group. See Table 7−2. Bit 0 is always = 0, therefore,
vector values are offset by two.
7−4 G[3:0] 0h This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector.
Table 7−2. Vector Interrupt Values
G[3:0]
(HEX)
I[2:0]
(HEX)
VECTOR
(HEX)
INTERRUPT SOURCE
0 0 00 No interrupt
1 0 10 Input endpoint-1 ACK
1 1 12 Input endpoint-2 ACK
1 2 14 Input endpoint-3 ACK
1 3 16 Input endpoint-4 ACK
1 4 18 Input endpoint-1 NACK
1 5 1A Input endpoint-2 NACK
1 6 1C Input endpoint-3 NACK
1 7 1E Input endpoint-4 NACK
2 0 20 Output endpoint-1 ACK
2 1 22 Output endpoint-2 ACK
2 2 24 Output endpoint-3 ACK
2 3 26 Output endpoint-4 ACK
2 4 28 Output endpoint-1 NACK
2 5 2A Output endpoint-2 NACK
2 6 2C Output endpoint-3 NACK
2 7 2E Output endpoint-4 NACK