Datasheet

Microcontroller Unit (MCU)
6−10
SLLS535E − April 2008TUSB6250
76543210
T7 T6 T5 T4 T3 T2 T1 T0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
7−0 T [7:0] 00h RTK timer value. The RTKTM register defines the RTK (INT6) interrupt intervals in 10 µs
increments. Note that a INT6 interrupt is generated only when T[7:0]>00 and EI6 is set (E16=1) in
the IE1: interrupt enable register (SFR at E8).
00h = RTK timer is disabled.
01h = Interrupt is generated every 10 µs
02h = Interrupt is generated every 20 µs
:
FFh = Interrupt is generated every 2,550 µs
6.3.3 WDCSR: Watchdog Timer Control and Status Register (at ESFR FBh)
A watchdog timer (WDT) with a 1-ms clock is provided. If the WDCSR register is not accessed for a period
of 128 ms, the WDT counter resets the MCU. When debugger logic is enabled and a break is detected, the
WDT is suspended until a jump-to-application is executed. at such point, the WDT resumes operation.
The WDT is enabled by default and can only be disabled by the MCU/firmware writing a pattern of 101010
into the WDD [5:0] bits. To avoid accidental reset by the WDT, the firmware has to ensure that it clears the WDT
before going into suspend.
The WDCSR register is cleared by a power-up reset only. The USB reset cannot clear the WDCSR register.
76543210
WDRI WDD5 WDD4 WDD3 WDD2 WDD1 WDD0 WDCES
R/C R/W R/W R/W R/W R/W R/W R/W
BIT
NAME RESET FUNCTION
0 WDCES 1 Watchdog timer counter clear and enabling status.
• For write access, this bit acts as the watchdog timer counter clear bit. The MCU must write a 1 to
this bit to prevent the WDT from resetting the device. If the MCU does not write a 1 in a period of
128 ms, the WDT resets the device. Writing a 0 has no effect on the WDT. The WDT is an 8-bit
counter using a 1-ms CLK.
• For read access, this bit acts as a status bit to indicate whether the watchdog timer is currently
enabled. A return value of 1 indicates the watchdog timer is enabled and a return value of 0
indicates the watchdog timer is disabled. A reset value of 1 indicates the watchdog timer is enabled
by default.
6−1 WDD[5:0] 000000 These bits are used to disable the watchdog timer. For the timer to be disabled, these bits must be set
to a special pattern of 101010. If any other pattern is present, the watchdog timer remains in operation.
These bits are read back as all 0.
7 WDRI 0 Watchdog reset indication bit. This bit indicates if the reset occurred due to a power-up reset or a
watchdog timer reset.
WDR = 0 A power-up reset occurred.
WDR = 1 A watchdog timeout reset occurred. To clear this bit, the MCU must write a 1. Writing a 0
has no effect.
6.3.4 MCUCNFG: MCU Configuration Register (at ESFR FCh)
The APP_MODE bit (bit 0) provides an indication for the MCU to distinguish whether it is currently running
in the boot-sequence mode or under firmware control. Once the boot code finishes the firmware download
and is ready to switch to firmware control, it sets this bit before relinquishing the control to the firmware. The
firmware should take extra care and never clear this bit.
When the WAKCLK bit in the USBMSK register and any one of the bits (bit 5 to 2) of the MCUCNFG register
are both enabled, any status change (for example, a media insertion/ejection or other remote wakeup event)
on the GPIO pins related to these four bits triggers a WAKCLK interrupt to the MCU, while the source of the
status change is logged in the USB wakeup reason register. Bits [5:2] act as the individual status change
(event) enable bits.