Datasheet

Architecture Overview
5−3
SLLS535E − April 2008 TUSB6250
The transaction handler manages the USB packet protocol requirement for the packets being received and
transmitted on the USB by the TUSB6250. For the received packet, the transaction handler checks the packet
identifier (PID) field to reveal the correct packet type from those defined by the USB 2.0 specification, such
as token, data, handshake, and special packets. It then checks the address, endpoint number, and the CRC
to ensure the received packet is a valid one being addressed to one of the enabled endpoints in the TUSB6250
controller. If the received packet is a data packet, it first notifies the UBM with the endpoint address and
direction information of the incoming data packet and then passes the following data payload. For the packet
being transmitted, the transaction handler gets the data from the UBM and generates the correct PID and CRC
as part of the transmit packet to be transmitted along with the data payload to the USB host. The
synchronization field (SYNC) is generated by the PHY. For the handshake packet, the UBM tells the
transaction handler what kind of handshake packet to send, as long as the CRC is valid. The transaction
handler then performs the task of sending the required handshake packet.
5.2.3 USB Buffer Manager (UBM)
The UBM is a high-performance DMA engine that manages the data movement between the transaction
handler and the TUSB6250 endpoint data buffer or sector FIFO (used by the ATA/ATAPI interface controller
for high-speed data transfer between the TUSB6250 controller and the storage device connected to its
ATA/ATAPI interface). For received packets, the UBM checks the endpoint address, direction information, and
loads (writes) the data payload into the appropriate endpoint data buffer or sector FIFO in the TUSB6250
controller. For the packet being transmitted, the UBM decodes the valid endpoint address, direction
information from the token packet provided by the transaction handler, and performs a read from the correct
endpoint data buffer or sector FIFO location in the TUSB6250 controller. The read-data is then passed to the
transaction handler to be processed and transferred to the USB host.
5.2.4 Embedded Microcontroller Unit (MCU)
The integrated MCU in the TUSB6250 controller is a high-speed 8-bit microcontroller core based on the
industry standard 8051 with certain improvements. The MCU operates at 60-MHz clock frequency with up to
30 MIPS performance.
The main functionality of the embedded MCU core of the TUSB6250 controller is to serve as a central
processing platform to allow the boot code (the microcode running at boot time) and firmware to perform the
device configuration and the activity control function by configuring and updating all the registers in the MCU,
USB, ATA/ATAPI, I
2
C, and the GPIO blocks.
5.2.5 ATA/ATAPI Interface Controller
The ATA/ATAPI interface controller is a high-performance DMA engine that continuously monitors the status
and manages the data movement between sector FIFO and the ATA/ATAPI storage device connected to the
TUSB6250 ATA/ATAPI interface, based on the ATA/ATAPI timing and protocol defined by the ATA/ATAPI-5
specification.
The ATA/ATAPI interface controller of the TUSB6250 controller offers both the flexibility of general MCU-based
bridge controllers and the performance of state-machine-based bridge controllers. It allows the MCU to move
the data manually between the endpoint data buffer and the ATA/ATAPI interface, while providing a
high-performance automatic data movement mode, in which the ATA/ATAPI interface controller and the UBM
work together to move the data quickly among the UBM, sector FIFO, and the ATA/ATAPI interface without
MCU involvement during the data stage of the bulk-only data transfer.
Some of the flexibilities offered by the TUSB6250 ATA/ATAPI interface controller include:
• Firmware-configurable IDE data transfer modes and timing that can be configured in the resolution of the
60-MHz clock cycle period
• Many hardware registers that provide information to assist the MCU to handle all 13 case conditions
correctly defined by the USB mass storage bulk-only transfer protocol specification.