Datasheet

Architecture Overview
5−2
SLLS535E − April 2008TUSB6250
5.2 Overview of Major Function Blocks
5.2.1 USB 2.0 UTMI-Compliant PHY
The main functions of the integrated USB 2.0 UTMI-compliant PHY are to convert the received serial data
stream from the USB host controller into parallel data packets that can be processed by the controller engine
of the TUSB6250 and to perform parallel-to-serial conversion for the data packets to be transmitted to the USB
host.
The integrated PHY communicates to the TUSB6250 controller parallel interface engine (PIE) through two
separate 8-bit-wide transmit and receive data buses and other handshake signals defined in the USB 2.0
UTMI specification version 1.4. The PHY also provides a 60-MHz clock signal to the PIE for synchronization.
It supports both high-speed (480 Mbps) USB signaling and full-speed (12 Mbps) signaling. This backward
compatibility allows the TUSB6250 controller to connect to any legacy USB full-speed hosts and hubs.
The PHY includes circuitry to monitor the line conditions for determining connection status, initialization, and
packet reception and transmission. The integrated PHY requires only an external 24-MHz crystal as a
reference. An external clock, with 1.8-V magnitude, can be provided to the XTAL1 pin instead of a crystal. An
internal oscillator drives an internal phase-locked loop (PLL), which generates the required 480-MHz
reference clock. The reference clock is internally divided to provide the clock signals used to control the
internal receive and transmit circuitry. The suspend function stops the operation of the PLL.
Data bits to be transmitted upstream are received on the 8-bit transmit bus from the PIE of the TUSB6250
controller and latched in synchronization with the 60-MHz clock. These bits are combined serially, encoded
and bit-stuffed as required, and transmitted to the USB host. During packet reception, the transmitters are
disabled. A clock signal and serial data bits are recovered from the received NRZI-encoded and bit-stuffed
information. The serial data bits are bit unstuffed, NRZI decoded, and deserialized. These bits are then
resynchronized to the local 60-MHz clock and sent to the PIE on the 8-bit wide receive bus.
The integrated PHY also provides the 60-MHz clock source to be used on all other blocks of the TUSB6250
controller. It contains two 3.3-V to 1.8-V voltage regulators to supply power for the PHY internal digital and
PLL circuitry.
An external 1.5-kΩ ±5% resistor must be placed between the RPU and AVDD pins. The resistor is required
for full-speed indication and connect signaling. Another external 5.9-kΩ ±1% resistor must be placed between
R1 and ground, which is used to mirror the current for internal analog circuitry reference.
5.2.2 USB 2.0 Parallel Interface Engine (PIE)
As shown in Figure 3−2, the PIE consists of four major blocks: a frame timer, a bus a monitor, a transaction
handler, and USB registers.
The bus monitor, as its name implies, monitors the USB differential signal line status through the USB 2.0
UTMI-compliant PHY. It informs the MCU via updating the UTMICFG:UTMI configuration status register
(XDATA at F00A) with the current line status information, such as high-speed or full-speed mode indication,
VBUS status, idle, and SE0 detection information. While interfacing with the PHY, the bus monitor is able to
perform connect or disconnect according to the configuration set up by the MCU and firmware. It detects and
generates the USB full-speed or high-speed handshake based on the protocol defined in the USB 2.0
specification and provides other capabilities such as suspend, resume, and remote wakeup. The bus monitor
also supports the required USB 2.0 high-speed compliance test modes.
The frame timer is responsible for tracking starts of frames (SOFs) from the bus monitor and generating the
USB frame number and microframe number, which is described in Section 8.6, USBFCL: USB Frame Counter
Low-Byte Register (XDATA at F00B) and Section 8.7, USBFCH: USB Frame Counter High-Byte Register
(XDATA at F00C).