Datasheet

Architecture Overview

5−1

SLLS535E − April 2008 TUSB6250

5 Architecture Overview

The overall functionality of the TUSB6250 is achieved by the combined interaction of major blocks or

subcontrollers as shown earlier in Figure 3−1. These major blocks include the USB 2.0 UTMI-compliant PHY,

USB 2.0 parallel interface engine (PIE), embedded microcontroller unit (MCU), USB buffer manager (UBM),

ATA/ATAPI interface controller, and the I

C interface controller.

5.1 Controller Brief Data Flow

As shown in Figure 5−1, the USB host controller, residing inside a PC, issues commands and/or data to the

TUSB6250-based external USB 2.0 mass storage device. The TUSB6250’s internal data flow is described

as follows (out-transaction example):

1. The USB 2.0 UTMI-compliant PHY receives serial data, either high-speed or full-speed, from the external

upstream USB host controller. The PHY processes this serial data stream and converts it into the

8-bit-wide parallel data packet based on the protocol defined in the USB 2.0 specification and the UTMI

specification.

2. The 8-bit wide parallel data packet, switching at 60-MHz, is passed to the USB 2.0 PIE block. The USB

2.0 PIE processes the data based on the defined USB packet protocol and passes the data to the UBM

block.

3. The UBM performs the endpoint address decoding and then passes the data packet to the addressed data

buffer location, which is either the endpoint buffer space or the sector FIFO space configured by the MCU

and its firmware. The section FIFO is the dedicated data buffer space directly accessible by the TUSB6250

controller’s internal high-performance ATA/ATAPI interface controller. The UBM also generates the

appropriate interrupt to inform the MCU of the arrival of the new packet.

4. The embedded MCU, either moves the data manually between the endpoint buffer and the ATA/ATAPI

interface, or enables automatic data movement between the sector FIFO and the ATA/ATAPI interface.

5. If the automatic data movement path is enabled, the data packet targeted to the storage device is loaded

automatically from the UBM into sector FIFO.

6. The ATA/ATAPI interface controller, which is a high-performance DMA engine, automatically moves the

data from sector FIFO to the storage device connected to its ATA/ATAPI interface with the data transfer

protocol and timing configured by the MCU and the firmware.

USB

Host

TUSB6250

ATA or ATAPI

Drive

Figure 5−1. TUSB6250 Typical Application Diagram