Datasheet

Device Parameter Information
4−3
SLLS535E − April 2008 TUSB6250
Table 4−1. Controller Terminal Description (80-Pin TQFP) (Continued)
TERMINAL I/O
DESCRIPTION
NAME NO. TYPE NOTES
DESCRIPTION
XTAL2 17 O (12) 24-MHz crystal output. This terminal has a 1.8-V LVCMOS output buffer.
XTAL1 18 I (11) 24-MHz crystal input. This terminal has a 1.8-V LVCMOS input buffer.
CONTROLLER POWER/GROUND
DGND 27,37,48,
56,66,75
GND Digital circuit ground terminals. Each ground terminal should be directly connected through a
low-impedance path to the ground plane.
DVDD 23,33,45,
53,63,77
PWR 3.3-V power-supply terminals for the internal I/O circuitry. Decoupling and filtering capacitors are
required on these power supply terminals.
DVDD18 32, 76 PWR 1.8-V power supply for the internal digital circuitry of the TUSB6250. An internal voltage
regulator generates this supply voltage when terminal DVREGEN
is asserted. When
DVREGEN
is de-asserted, 1.8 V must be supplied externally. Bypass capacitors to ground are
required on these pins.
SUSPEND 80 O (1) Suspend status indication. This terminal is low during normal operation and active high during
suspend. It can be used for external logic power-down operations.
ATA/ATAPI INTERFACE
CS1 25 O (2)(9) ATA/ATAPI: Drive chip select-1. Used to select the control block registers defined by the
ATA/ATAPI-5 specification. This terminal should be connected to the corresponding pin of the
ATA/ATAPI interface connector on the end-product PCB.
CS0 26 O (2)(9) ATA/ATAPI: Drive chip select-0. Used to select the command block registers defined by the
ATA/ATAPI-5 specification. This terminal should be connected to the corresponding pin of the
ATA/ATAPI interface connector on the end-product PCB.
DA [2:0] 28, 31,
29
O (2)(9) ATA/ATAPI: These three address lines are used to select the ATA/ATAPI drive registers as
defined by the ATA/ATAPI-5 specification. These terminals should be connected to the
corresponding pins of the ATA/ATAPI interface connector on the end-product PCB.
DD [15:0] 41,43,46,
49,51,54,
57,59,60,
58,55,52,
50,47,44,
42
I/O (2)(5)
(10)
ATA/ATAPI: 16-bit I/O data bus. These terminals are all 5-V fail-safe with internal controllable
pulldown resistors. These terminals should be connected to the corresponding pins of the
ATA/ATAPI interface connector on the end-product PCB.
DMACK 35 O (2)(9) ATA/ATAPI: DMA acknowledge. This terminal should be connected to the corresponding pin of
the ATA/ATAPI interface connector on the end-product PCB.
DMARQ 40 I (5)(10) ATA/ATAPI: DMA request. This 5-V fail-safe terminal has an internal controllable pulldown
resistor. The power-up default is the pulldown resistor enabled. This terminal should be
connected to the corresponding pin of the ATA/ATAPI interface connector on the end-product
PCB.
DIOR 38 O (2)(9) ATA/ATAPI: Read strobe signal. This terminal should be connected to the corresponding pin of
the ATA/ATAPI interface connector on the end-product PCB.
DIOW 39 O (2)(9) ATA/ATAPI: Write strobe signal. This terminal should be connected to the corresponding pin of
the ATA/ATAPI interface connector on the end-product PCB.
INTRQ 34 I (5)(9) ATA/ATAPI: Interrupt request. The ATA device asserts this signal when it has a pending interrupt.
This 5-V fail-safe terminal has internal configurable pullup and pulldown resistors. The power-up
default is the pulldown resistor enabled. This terminal should be connected to the corresponding
pin of the ATA/ATAPI interface connector on the end-product PCB.
IORDY 36 I (5)(9) ATA/ATAPI: Channel ready. This 5-V fail-safe terminal has internal configurable pullup and
pulldown resistors. The power-up default is the pullup resistor enabled. This terminal should be
connected to the corresponding pin of the ATA/ATAPI interface connector on the end-product
PCB.
P3.6 30 I/O (2)(5)
(9)
5-V fail-safe general-purpose I/O with internal configurable pullup and pulldown resistors. This
terminal can be used as a GPIO or PDIAG
function to be implemented by the end-product
developer’s custom firmware. After power-on reset, this terminal defaults as input with the
internal pullup resistor enabled. The MCU can reconfigure the pullup and pulldown resistors, if
desired.