Datasheet

Device Parameter Information
4−2
SLLS535E − April 2008TUSB6250
4.2 Terminal Functions
Table 4−1. Controller Terminal Description (80-Pin TQFP)
TERMINAL I/O
DESCRIPTION
NAME NO. TYPE NOTES
DESCRIPTION
INTEGRATED USB 2.0 UTMI-COMPLIANT PHY
AGND 7, 10,
16
GND Analog ground. All ground terminals should be connected together externally through a
low-impedance path. All bypass capacitors to PLLVDD18, UDVDD18, and AVDD should connect to
ground through a low-impedance path.
AVDD 6, 13 PWR 3.3-V supply voltage for the integrated USB 2.0 UTMI-compliant PHY’s internal analog circuitry. This
supply is also regulated internally down to 1.8 V for use by the PHY’s internal digital circuitry when
VREGEN is asserted. Bypass capacitors to ground are required on these terminals.
DM 15 I/O USB differential data minus
DP 14 I/O USB differential data plus
PLLVDD18 8 PWR 1.8-V supply for the internal PLL circuitry of the integrated USB 2.0 UTMI-compliant PHY. An internal
voltage regulator generates this supply when terminal VREGEN
is asserted. When VREGEN is
de-asserted, 1.8 V must be supplied externally. Bypass capacitance is required on this terminal
regardless of the state of VREGEN. It is recommended that the capacitance on this terminal not be
less then 1 µF.
R1 11 I/O External reference resistor. An internally generated band-gap voltage is placed on this resistor. The
current through the resistor is mirrored internally to generate the current and voltage used by the
internal analog circuitry. This pin has nominally 1.21 V dc. An external 5.9-kΩ ±1% resistor must be
placed between this terminal and ground. It is recommended that the resistor be placed as close as
possible to this terminal with a minimal trace length to ground.
RPU 5 I/O Pullup resistor connection. This terminal is used to attach and detach the full-speed indicator resistor
electrically to/from the DP signal line. An external 1.5-kΩ ±5% resistor must be placed between RPU
and AVDD.
UDVDD18 9 PWR 1.92-V supply for the internal digital circuitry of the integrated USB 2.0 UTMI-compliant PHY. An
internal voltage regulator generates this supply when terminal VREGEN
is asserted. When VREGEN
is de-asserted, 1.92 V must be supplied externally. Bypass capacitance is required on this terminal
regardless of the state of VREGEN
. It is recommended that the capacitance on this terminal not be
less then 1 µF. Do not connect the UDVDD18 terminal to the PLLVDD18 or DVDD18 terminal, because
their voltages differ.
VREGEN 12 I Voltage regulator enable (active-low). Two internal 3.3-V to 1.8-V voltage regulators supply the digital
and PLL circuitry when this terminal is asserted. When this terminal is de-asserted, the voltage
regulators are disabled and 1.8 V must be supplied externally. TI recommends that this terminal be
tied to ground during normal operation.
CONTROLLER GENERAL
DVREGEN 1 I (4) This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator in the TUSB6250’s
digital core. When this terminal is de-asserted, the voltage regulator is disabled and 1.8 V must be
supplied externally. TI recommends that this terminal be tied to ground during normal operation.
P3.0/SIN 79 I/O (1)(6)
(8)
This dual-function terminal can be used as either GPIO or the serial data input of the integrated 8051
microcontroller serial port. The power-up default is to have its internal pullup activated.
P3.1/SOUT 78 I/O (1)(6)
(8)
This dual-function terminal can be used as either GPIO or the serial data output of the integrated 8051
microcontroller serial port. The power-up default is to have its internal pullup activated.
RSTI 2 I (4) The TUSB6250 master reset signal. This active-low terminal is the master reset signal for the
TUSB6250. See Section 13.2, Reset Timing Reference, for detailed reset timing information.
SCL 21 O (7)(8) Master I
2
C controller: clock signal for external I
2
C serial EEPROM. The internal 100-µA pullup resistor
on this terminal is always enabled.
SDA 22 I/O (4)(7)
(8)
Master I
2
C controller: data signal for external I
2
C serial EEPROM. The internal 100-µA pullup resistor
on this terminal is always enabled.
TSTMODE1
TSTMODE2
19
20
I (4)(8) These terminals are used for factory test of the TUSB6250. During normal operation, these terminals
must be left open.
VBUS 4 I (5)(10) This terminal monitors the status of the USB upstream VBUS. It has the internal pulldown resistor
enabled as the power-on reset default.